riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

intel_synth: Make family explicit and match 

The help and code default to MAX10 for the family, however the couple of
if ladders defaulted to cycloneive. Fix this inconsistency and the next
patch will clean it up.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Ben Widawsky 2019-07-08 12:24:24 -07:00 committed by Dan Ravensloft
parent 060e77c09b
commit 809b94a67b
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/intel/synth_intel.cc
View File

@ -176,8 +176,10 @@ struct SynthIntelPass : public ScriptPass {
run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
else if (check_label("family") && family_opt == "cycloneiv")
run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
else
else if (check_label("family") && family_opt == "cycloneive")
run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
else
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
// Misc and common cells
run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
@ -236,8 +238,10 @@ struct SynthIntelPass : public ScriptPass {
run("techmap -map +/intel/cyclone10/cells_map.v");
else if (family_opt == "cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");
else
else if (family_opt == "cycloneive")
run("techmap -map +/intel/cycloneive/cells_map.v");
else
log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
run("dffinit -highlow -ff dffeas q power_up");
run("clean -purge");
}