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Merge remote-tracking branch 'origin/master' into xc7dsp

This commit is contained in:
Eddie Hung 2019-07-15 09:49:41 -07:00
parent b33ecd2a74 a97d30d2f8
commit 146451a767
16 changed files with 639 additions and 30 deletions
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10
backends/verilog/verilog_backend.cc
View File

@ -222,7 +222,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
case RTLIL::S1: bin_digits.push_back('1'); break;
case RTLIL::Sx: bin_digits.push_back('x'); break;
case RTLIL::Sz: bin_digits.push_back('z'); break;
case RTLIL::Sa: bin_digits.push_back('z'); break;
case RTLIL::Sa: bin_digits.push_back('?'); break;
case RTLIL::Sm: log_error("Found marker state in final netlist.");
}
}
@ -251,6 +251,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
hex_digits.push_back('z');
continue;
}
if (bit_3 == '?' || bit_2 == '?' || bit_1 == '?' || bit_0 == '?') {
if (bit_3 != '?' || bit_2 != '?' || bit_1 != '?' || bit_0 != '?')
goto dump_bin;
hex_digits.push_back('?');
continue;
}
int val = 8*(bit_3 - '0') + 4*(bit_2 - '0') + 2*(bit_1 - '0') + (bit_0 - '0');
hex_digits.push_back(val < 10 ? '0' + val : 'a' + val - 10);
}
@ -270,7 +276,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
case RTLIL::S1: f << stringf("1"); break;
case RTLIL::Sx: f << stringf("x"); break;
case RTLIL::Sz: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("z"); break;
case RTLIL::Sa: f << stringf("?"); break;
case RTLIL::Sm: log_error("Found marker state in final netlist.");
}
}

4
frontends/aiger/aigerparse.cc
View File

@ -1062,8 +1062,8 @@ struct AigerFrontend : public Frontend {
if (module_name.empty()) {
#ifdef _WIN32
char fname[_MAX_FNAME];
_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
module_name = fname;
_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */);
module_name = fname;
#else
char* bn = strdup(filename.c_str());
module_name = RTLIL::escape_id(bn);

2
passes/techmap/abc9.cc
View File

@ -29,7 +29,7 @@
"&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\
"&st; &if -g -K 6; &synch2; &if {W}; &save; &load"
#else
#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l"
#define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; &mfs; &ps -l"
#endif

19
passes/techmap/attrmap.cc
View File

@ -263,6 +263,25 @@ struct AttrmapPass : public Pass {
for (auto cell : module->selected_cells())
attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
for (auto proc : module->processes)
{
if (!design->selected(module, proc.second))
continue;
attrmap_apply(stringf("%s.%s", log_id(module), log_id(proc.first)), actions, proc.second->attributes);
std::vector<RTLIL::CaseRule*> all_cases = {&proc.second->root_case};
while (!all_cases.empty()) {
RTLIL::CaseRule *cs = all_cases.back();
all_cases.pop_back();
attrmap_apply(stringf("%s.%s (case)", log_id(module), log_id(proc.first)), actions, cs->attributes);
for (auto &sw : cs->switches) {
attrmap_apply(stringf("%s.%s (switch)", log_id(module), log_id(proc.first)), actions, sw->attributes);
all_cases.insert(all_cases.end(), sw->cases.begin(), sw->cases.end());
}
}
}
}
}
}

16
techlibs/ice40/synth_ice40.cc
View File

@ -67,9 +67,6 @@ struct SynthIce40Pass : public ScriptPass
log(" -retime\n");
log(" run 'abc' with -dff option\n");
log("\n");
log(" -relut\n");
log(" combine LUTs after synthesis\n");
log("\n");
log(" -nocarry\n");
log(" do not use SB_CARRY cells in output netlist\n");
log("\n");
@ -78,7 +75,7 @@ struct SynthIce40Pass : public ScriptPass
log("\n");
log(" -dffe_min_ce_use <min_ce_use>\n");
log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
log(" than min_ce_use SB_DFFE*in output netlist\n");
log(" than min_ce_use SB_DFFE* in output netlist\n");
log("\n");
log(" -nobram\n");
log(" do not use SB_RAM40_4K* cells in output netlist\n");
@ -106,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
}
string top_opt, blif_file, edif_file, json_file, abc, device_opt;
bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr;
int min_ce_use;
void clear_flags() YS_OVERRIDE
@ -122,7 +119,6 @@ struct SynthIce40Pass : public ScriptPass
dsp = false;
flatten = true;
retime = false;
relut = false;
noabc = false;
abc2 = false;
vpr = false;
@ -175,7 +171,7 @@ struct SynthIce40Pass : public ScriptPass
continue;
}
if (args[argidx] == "-relut") {
relut = true;
// removed, opt_lut is always run
continue;
}
if (args[argidx] == "-nocarry") {
@ -347,10 +343,8 @@ struct SynthIce40Pass : public ScriptPass
run(abc + " -dress -lut 4", "(skip if -noabc)");
}
run("clean");
if (relut || help_mode) {
run("ice40_unlut", " (only if -relut)");
run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
}
run("ice40_unlut");
run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3");
}
if (check_label("map_cells"))

15
techlibs/xilinx/Makefile.inc
View File

@ -5,6 +5,8 @@ GENFILES += techlibs/xilinx/brams_init_36.vh
GENFILES += techlibs/xilinx/brams_init_32.vh
GENFILES += techlibs/xilinx/brams_init_18.vh
GENFILES += techlibs/xilinx/brams_init_16.vh
GENFILES += techlibs/xilinx/brams_init_9.vh
GENFILES += techlibs/xilinx/brams_init_8.vh
EXTRA_OBJS += techlibs/xilinx/brams_init.mk
.SECONDARY: techlibs/xilinx/brams_init.mk
@ -18,13 +20,18 @@ techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk
techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
@ -40,4 +47,6 @@ $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh))
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh))

16
techlibs/xilinx/brams_init.py
View File

@ -1,5 +1,17 @@
#!/usr/bin/env python3
with open("techlibs/xilinx/brams_init_9.vh", "w") as f:
for i in range(4):
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
for k in range(4, 256, 4):
init_snippets[k] = "\n " + init_snippets[k]
print(".INITP_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
for i in range(32):
init_snippets = [" INIT[%3d*9 +: 8]" % (k+32*i,) for k in range(31, -1, -1)]
for k in range(4, 32, 4):
init_snippets[k] = "\n " + init_snippets[k]
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
with open("techlibs/xilinx/brams_init_18.vh", "w") as f:
for i in range(8):
init_snippets = [" INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
@ -24,6 +36,10 @@ with open("techlibs/xilinx/brams_init_36.vh", "w") as f:
init_snippets[k] = "\n " + init_snippets[k]
print(".INIT_%02X({%s})," % (i, ",".join(init_snippets)), file=f)
with open("techlibs/xilinx/brams_init_8.vh", "w") as f:
for i in range(32):
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
with open("techlibs/xilinx/brams_init_16.vh", "w") as f:
for i in range(64):
print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)

4
techlibs/xilinx/cells_sim.v
View File

@ -226,7 +226,7 @@ module FDRE (output reg Q, input C, CE, D, R);
endmodule
module FDSE (output reg Q, input C, CE, D, S);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
@ -252,7 +252,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
endmodule
module FDPE (output reg Q, input C, CE, D, PRE);
parameter [0:0] INIT = 1'b0;
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;

8
techlibs/xilinx/ff_map.v
View File

@ -33,10 +33,10 @@ module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPL
module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
`endif

25
techlibs/xilinx/synth_xilinx.cc
View File

@ -244,8 +244,13 @@ struct SynthXilinxPass : public ScriptPass
run("read_verilog -lib +/xilinx/cells_xtra.v");
if (!nobram || help_mode)
run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
if (help_mode) {
run("read_verilog -lib +/xilinx/{family}_brams_bb.v");
} else if (family == "xc6s") {
run("read_verilog -lib +/xilinx/xc6s_brams_bb.v");
} else if (family == "xc7") {
run("read_verilog -lib +/xilinx/xc7_brams_bb.v");
}
run(stringf("hierarchy -check %s", top_opt.c_str()));
}
@ -292,9 +297,19 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("bram", "(skip if '-nobram')")) {
if (!nobram || help_mode) {
run("memory_bram -rules +/xilinx/brams.txt");
run("techmap -map +/xilinx/brams_map.v");
if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v");
} else if (!nobram) {
if (family == "xc6s") {
run("memory_bram -rules +/xilinx/xc6s_brams.txt");
run("techmap -map +/xilinx/xc6s_brams_map.v");
} else if (family == "xc7") {
run("memory_bram -rules +/xilinx/xc7_brams.txt");
run("techmap -map +/xilinx/xc7_brams_map.v");
} else {
log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str());
}
}
}

84
techlibs/xilinx/xc6s_brams.txt Normal file
View File

@ -0,0 +1,84 @@
bram $__XILINX_RAMB8BWER_SDP
init 1
abits 8
dbits 36
groups 2
ports 1 1
wrmode 0 1
enable 1 4
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB16BWER_TDP
init 1
abits 9 @a9d36
dbits 36 @a9d36
abits 10 @a10d18
dbits 18 @a10d18
abits 11 @a11d9
dbits 9 @a11d9
abits 12 @a12d4
dbits 4 @a12d4
abits 13 @a13d2
dbits 2 @a13d2
abits 14 @a14d1
dbits 1 @a14d1
groups 2
ports 1 1
wrmode 0 1
enable 1 4 @a9d36
enable 1 2 @a10d18
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB8BWER_TDP
init 1
abits 9 @a9d18
dbits 18 @a9d18
abits 10 @a10d9
dbits 9 @a10d9
abits 11 @a11d4
dbits 4 @a11d4
abits 12 @a12d2
dbits 2 @a12d2
abits 13 @a13d1
dbits 1 @a13d1
groups 2
ports 1 1
wrmode 0 1
enable 1 2 @a9d18
enable 1 1 @a10d9 @a11d4 @a12d2 @a13d1
transp 0 0
clocks 2 3
clkpol 2 3
endbram
match $__XILINX_RAMB8BWER_SDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB16BWER_TDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
or_next_if_better
endmatch
match $__XILINX_RAMB8BWER_TDP
min bits 4096
min efficiency 5
shuffle_enable B
make_transp
endmatch

211
techlibs/xilinx/xc6s_brams_bb.v Normal file
View File

@ -0,0 +1,211 @@
module RAMB8BWER (
input CLKAWRCLK,
input CLKBRDCLK,
input ENAWREN,
input ENBRDEN,
input REGCEA,
input REGCEBREGCE,
input RSTA,
input RSTBRST,
input [12:0] ADDRAWRADDR,
input [12:0] ADDRBRDADDR,
input [15:0] DIADI,
input [15:0] DIBDI,
input [1:0] DIPADIP,
input [1:0] DIPBDIP,
input [1:0] WEAWEL,
input [1:0] WEBWEU,
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter RAM_MODE = "TDP";
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter integer DATA_WIDTH_A = 0;
parameter integer DATA_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter EN_RSTRAM_A = "TRUE";
parameter EN_RSTRAM_B = "TRUE";
parameter INIT_A = 18'h000000000;
parameter INIT_B = 18'h000000000;
parameter SRVAL_A = 18'h000000000;
parameter SRVAL_B = 18'h000000000;
parameter RST_PRIORITY_A = "CE";
parameter RST_PRIORITY_B = "CE";
parameter RSTTYPE = "SYNC";
parameter SIM_COLLISION_CHECK = "ALL";
endmodule
module RAMB16BWER (
input CLKA,
input CLKB,
input ENA,
input ENB,
input REGCEA,
input REGCEB,
input RSTA,
input RSTB,
input [13:0] ADDRA,
input [13:0] ADDRB,
input [31:0] DIA,
input [31:0] DIB,
input [3:0] DIPA,
input [3:0] DIPB,
input [3:0] WEA,
input [3:0] WEB,
output [31:0] DOA,
output [31:0] DOB,
output [3:0] DOPA,
output [3:0] DOPB
);
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter integer DATA_WIDTH_A = 0;
parameter integer DATA_WIDTH_B = 0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter EN_RSTRAM_A = "TRUE";
parameter EN_RSTRAM_B = "TRUE";
parameter INIT_A = 36'h000000000;
parameter INIT_B = 36'h000000000;
parameter SRVAL_A = 36'h000000000;
parameter SRVAL_B = 36'h000000000;
parameter RST_PRIORITY_A = "CE";
parameter RST_PRIORITY_B = "CE";
parameter RSTTYPE = "SYNC";
parameter SIM_COLLISION_CHECK = "ALL";
endmodule

255
techlibs/xilinx/xc6s_brams_map.v Normal file
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@ -0,0 +1,255 @@
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [9215:0] INIT = 9216'bx;
input CLK2;
input CLK3;
input [7:0] A1ADDR;
output [35:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
input [35:0] B1DATA;
input [3:0] B1EN;
wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB8BWER #(
.RAM_MODE("SDP"),
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_9.vh"
) _TECHMAP_REPLACE_ (
.DOBDO(DO[31:16]),
.DOADO(DO[15:0]),
.DOPBDOP(DOP[3:2]),
.DOPADOP(DOP[1:0]),
.DIBDI(DI[31:16]),
.DIADI(DI[15:0]),
.DIPBDIP(DIP[3:2]),
.DIPADIP(DIP[1:0]),
.WEBWEU(B1EN[3:2]),
.WEAWEL(B1EN[1:0]),
.ADDRAWRADDR(B1ADDR_13),
.CLKAWRCLK(CLK3 ^ !CLKPOL3),
.ENAWREN(|1),
.REGCEA(|0),
.RSTA(|0),
.ADDRBRDADDR(A1ADDR_13),
.CLKBRDCLK(CLK2 ^ !CLKPOL2),
.ENBRDEN(A1EN),
.REGCEBREGCE(|1),
.RSTB(|0)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
wire [3:0] B1EN_4 = {4{B1EN}};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOB;
wire [3:0] DOPB;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB16BWER #(
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_18.vh"
) _TECHMAP_REPLACE_ (
.DIA(32'd0),
.DIPA(4'd0),
.DOA(DO[31:0]),
.DOPA(DOP[3:0]),
.ADDRA(A1ADDR_14),
.CLKA(CLK2 ^ !CLKPOL2),
.ENA(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEA(4'b0),
.DIB(DI),
.DIPB(DIP),
.DOB(DOB),
.DOPB(DOPB),
.ADDRB(B1ADDR_14),
.CLKB(CLK3 ^ !CLKPOL3),
.ENB(|1),
.REGCEB(|0),
.RSTB(|0),
.WEB(B1EN_4)
);
end else begin
RAMB16BWER #(
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_16.vh"
) _TECHMAP_REPLACE_ (
.DIA(32'd0),
.DIPA(4'd0),
.DOA(DO[31:0]),
.DOPA(DOP[3:0]),
.ADDRA(A1ADDR_14),
.CLKA(CLK2 ^ !CLKPOL2),
.ENA(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEA(4'b0),
.DIB(DI),
.DIPB(DIP),
.DOB(DOB),
.DOPB(DOPB),
.ADDRB(B1ADDR_14),
.CLKB(CLK3 ^ !CLKPOL3),
.ENB(|1),
.REGCEB(|0),
.RSTB(|0),
.WEB(B1EN_4)
);
end endgenerate
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [9215:0] INIT = 9216'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
wire [1:0] B1EN_2 = {2{B1EN}};
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB8BWER #(
.RAM_MODE("TDP"),
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_9.vh"
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRAWRADDR(A1ADDR_13),
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
.ENAWREN(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEAWEL(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBRDADDR(B1ADDR_13),
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTB(|0),
.WEBWEU(B1EN_2)
);
end else begin
RAMB8BWER #(
.RAM_MODE("TDP"),
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_8.vh"
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRAWRADDR(A1ADDR_13),
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
.ENAWREN(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEAWEL(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBRDADDR(B1ADDR_13),
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTB(|0),
.WEBWEU(B1EN_2)
);
end endgenerate
endmodule

0
techlibs/xilinx/brams.txt → techlibs/xilinx/xc7_brams.txt
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techlibs/xilinx/brams_bb.v → techlibs/xilinx/xc7_brams_bb.v
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0
techlibs/xilinx/brams_map.v → techlibs/xilinx/xc7_brams_map.v
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