mirror of https://github.com/YosysHQ/yosys.git
Fix typo and comments
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c91cb73562
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c864995343
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@ -204,7 +204,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
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end
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else if (A_WIDTH <= 4) begin
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// Rather than extend with 1'bx which gets flattened to 1'b0
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// causing the "don't care" status to get lost, extend with MSB
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// causing the "don't care" status to get lost, extend with MSBs
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// so that we can recognise again later when mapping MUXF78
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wire [4-1:0] Ax;
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if (A_WIDTH == 4)
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@ -215,7 +215,7 @@ module \$__XILINX_SHIFTX (A, B, Y);
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end
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else if (A_WIDTH <= 8) begin
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// Rather than extend with 1'bx which gets flattened to 1'b0
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// causing the "don't care" status to get lost, extend with MSB
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// causing the "don't care" status to get lost, extend with MSBs
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// so that we can recognise again later when mapping MUXF78
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wire [8-1:0] Ax;
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if (A_WIDTH == 8)
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@ -230,13 +230,13 @@ module \$__XILINX_SHIFTX (A, B, Y);
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end
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else if (A_WIDTH <= 16) begin
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// Rather than extend with 1'bx which gets flattened to 1'b0
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// causing the "don't care" status to get lost, extend with MSB
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// causing the "don't care" status to get lost, extend with MSBs
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// so that we can recognise again later when mapping MUXF78
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wire [16-1:0] Ax;
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if (A_WIDTH == 16)
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assign Ax = A;
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else
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assign Ax = {A[7-:8-A_WIDTH], A};
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assign Ax = {A[7-:16-A_WIDTH], A};
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wire T0 = B[2] ? B[3] ? Ax[12] : Ax[4]
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: B[3] ? Ax[ 8] : Ax[0];
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wire T1 = B[2] ? B[3] ? Ax[13] : Ax[5]
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