mirror of https://github.com/YosysHQ/yosys.git
Update abc_box_id numbering
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699d8e3939
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@ -23,7 +23,7 @@
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module \$__ABC_FF_ (input C, D, output Q);
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endmodule
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(* abc_box_id = 6, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
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(* abc_box_id = 7, lib_whitebox, abc_flop = "FDRE", abc_flop_q = "Q", abc_flop_d = "D", abc_flop_past_q = "\\$pastQ" *)
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module \$__ABC_FDRE (output Q, input C, CE, D, R, \$pastQ );
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parameter [0:0] INIT = 1'b0;
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//parameter [0:0] IS_C_INVERTED = 1'b0;
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@ -54,20 +54,20 @@ RAM128X1D 6 0 17 2
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# Inputs: C CE D R \$pastQ
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# Outputs: Q
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FDRE 6 1 5 1
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FDRE 7 1 5 1
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- 109 -46 358 0
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# Inputs: C CE D S \$pastQ
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# Outputs: Q
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FDSE 7 0 5 1
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FDSE 8 0 5 1
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- 109 -46 358 0
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# Inputs: C CE CLR D \$pastQ
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# Outputs: Q
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FDCE 8 0 5 1
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FDCE 9 0 5 1
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- 109 - -46 0
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# Inputs: C CE D PRE \$pastQ
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# Outputs: Q
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FDPE 9 0 5 1
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FDPE 10 0 5 1
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- 109 -46 - 0
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