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OpenFPGA
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418 Commits

Author SHA1 Message Date
Baudouin Chauviere a0f1f8d163 Fix when explicit verilog is NOT used 2019-07-12 10:39:31 -06:00
tangxifan f0ecc51b51 bug fixing to resolve the conflicts between explicit port map and standard cell map 2019-07-12 10:38:20 -06:00
AurelienUoU e65cf9f5fd Update ERI-demo 2019-07-12 08:55:19 -06:00
Baudouin Chauviere 40d3460bac Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-11 22:13:30 -06:00
Baudouin Chauviere e461cd0b99 Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-11 22:09:49 -06:00
Baudouin Chauviere 1431ee2f82 Fix Explicit verilog 2019-07-11 22:09:34 -06:00
tangxifan cffdebd912 bug fixed for the tileable RR graph generator for heterogeneous blocks 2019-07-11 21:02:09 -06:00
Baudouin Chauviere c9b84f61c9 Hot fix 2019-07-11 17:39:02 -06:00
Baudouin Chauviere d0cd5a2bc1 Hot fix 2019-07-11 17:27:31 -06:00
tangxifan 9c203ca4d2 bug fixing in SDC generator 2019-07-11 17:10:08 -06:00
Baudouin Chauviere f4be375637 Latest version explicit 2019-07-11 14:33:56 -06:00
tangxifan 31749fe62b fix bugs in fpga_flow.pl 2019-07-10 21:12:00 -06:00
tangxifan a90316e9f4 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-10 15:13:46 -06:00
tangxifan acee0161c7 Merge branch 'tileable_routing' into dev 2019-07-10 15:13:24 -06:00
Baudouin Chauviere 6441f2ebe7 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-10 14:16:55 -06:00
Baudouin Chauviere 0a978db866 Fix regression test 2019-07-10 14:16:34 -06:00
tangxifan b7f9831bd2 add statistics for unique GSBs 2019-07-10 13:08:03 -06:00
tangxifan c6a4d29ed8 Merge branch 'tileable_routing' into dev 2019-07-10 12:05:43 -06:00
tangxifan 57ae5dbbec bug fixing for rectangle FPGA sizes 2019-07-09 20:47:52 -06:00
tangxifan edfe3144c3 update profiling, found where runtime is lost 2019-07-09 20:28:01 -06:00
tangxifan 737cc2874f Merge branch 'tileable_routing' into dev 2019-07-09 17:42:44 -06:00
tangxifan 65f696c1d7 fix critical bugs in rectangle floorplan 2019-07-09 17:41:20 -06:00
Baudouin Chauviere 4ca0967453 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-09 14:35:51 -06:00
Baudouin Chauviere 792ba23f4f Correction pre-merge 2019-07-09 14:34:34 -06:00
Baudouin Chauviere 589f58b55e Regression test succeeded 2019-07-09 09:18:06 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
tangxifan 5d5e09fcdb minor fix in trying to accelerate the unique routing functions 2019-07-08 17:12:36 -06:00
Baudouin Chauviere df0a3d23a3 Correction top module 2019-07-08 10:23:14 -06:00
Baudouin Chauviere ae05c553d5 Top module done 2019-07-08 09:48:33 -06:00
tangxifan 76fefdb876 bug fixing in Fc_in and be serious in the performance of rr_graph 2019-07-05 16:23:15 -06:00
tangxifan c62762ce59 bug fixing in assign ipins to tracks using Fc_in 2019-07-05 13:42:22 -06:00
tangxifan 64d8e9663a minor fix to satisfy Fc_in and Fc_out 2019-07-05 13:13:35 -06:00
tangxifan 3077efa74f add option to compact tileable routing arch 2019-07-04 17:13:34 -06:00
tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan b79d276ea9 add profiling to fpga_x2p_setup 2019-07-03 14:44:54 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
tangxifan 44301bfd77 updated SPICE generator to avoid issues on clb2clb_direct 2019-07-02 09:01:52 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 15c536e9b4 minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Ganesh Gore 11e6350214 Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev 2019-06-27 14:22:40 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
tangxifan 8edd85c9fc keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
tangxifan 711e369fe7 fixing bugs in the SDC generator and report_timing 2019-06-26 18:09:09 -06:00
tangxifan 0fe54d87d5 fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 7d85eb544d start fixing bugs for SDC generator when using tileable arch 2019-06-26 16:48:17 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00
tangxifan d2ed82d14d Merge branch 'tileable_routing' into multimode_clb 2019-06-26 15:00:39 -06:00
tangxifan 57616361c2 fixed critical bugs in cb configuration port indices 2019-06-26 14:58:52 -06:00
Baudouin Chauviere d2bd2be76b Warnings correction in the make sequence 2019-06-26 14:33:12 -06:00
Baudouin Chauviere 87ddca9f57 commiting current work. Stable but function not implemented yet 2019-06-26 14:22:02 -06:00
tangxifan 42f85004b6 fix bugs in finding the ending SB of a rr_node 2019-06-26 14:13:41 -06:00
tangxifan 9b6a4b39bb Merge branch 'tileable_routing' into multimode_clb 2019-06-26 11:36:08 -06:00
tangxifan c879e7f6c5 fixed a critical bug when instanciating Connection blocks 2019-06-26 11:33:02 -06:00
Baudouin Chauviere b7c2954b91 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-26 10:51:55 -06:00
Baudouin Chauviere 8f21a3b177 Memory leakage correction 2019-06-26 10:50:38 -06:00
tangxifan d50fb7ee19 fixed the bug in determine passing wires for rr_gsb 2019-06-26 10:50:23 -06:00
AurelienUoU ec504049ef Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
tangxifan a3670bb752 Merge branch 'multimode_clb' into tileable_routing 2019-06-26 09:45:04 -06:00
Baudouin Chauviere 56557b94e7 Bug Fix 2019-06-26 08:53:46 -06:00
tangxifan 3c0ef2067d fixed critical bugs in pass_tracks identification and update regression test for tileable arch 2019-06-25 21:59:38 -06:00
Baudouin Chauviere bb250ddef9 Bug fix in cpp 2019-06-25 16:47:10 -06:00
Ganesh Gore 6d3066174b Merge remote-tracking branch 'origin/fpga_spice' into ganesh_dev 2019-06-25 15:12:13 -06:00
tangxifan 4d3b5f12b4 fixed bugs for UNIVERSAL and WILTON switch blocks 2019-06-25 14:15:29 -06:00
Baudouin Chauviere 332ce17f03 Division between horizontal and vertical analysis 2019-06-25 13:44:41 -06:00
tangxifan a88263a4c2 update rr_block writer to include IPINs in XML files 2019-06-25 11:17:22 -06:00
tangxifan 785b560bd5 sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now 2019-06-24 22:46:56 -06:00
tangxifan fd301eeb66 many bug fixing and now start improving the routability of tileable rr_graph 2019-06-24 17:33:29 -06:00
tangxifan 0d62661c71 bug fixing and spot critical bugs in directlist parser 2019-06-23 20:52:38 -06:00
tangxifan cdd4af9c58 vpr likes the tileable rr_graph while fpga_x2p does not 2019-06-23 18:11:13 -06:00
tangxifan 59df305668 bug fixing and reorganize rr_graph builder source files 2019-06-23 16:40:13 -06:00
tangxifan 2837f44df2 bug fixing for tileable rr_graph generator. 2019-06-22 20:41:06 -06:00
tangxifan 7c38b32eb1 keep bug fixing for tileable rr_graph generator 2019-06-21 22:51:11 -06:00
tangxifan 1b91c32121 Merge branch 'multimode_clb' into tileable_routing 2019-06-21 17:59:55 -06:00
tangxifan 41954056ce many bug fixing for tileable rr_graph generator. Still debugging 2019-06-21 17:58:46 -06:00
AurelienUoU 0a42f6a796 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-21 15:47:14 -06:00
AurelienUoU c0d7099cd6 Allow CB on top of blocks with height > 1 2019-06-21 15:46:05 -06:00
tangxifan d48fd959a9 keep bug fixing for tileable rr_graph generator 2019-06-20 22:30:26 -06:00
tangxifan 548242b368 plug-in tileable rr generator which can be enable by a XML property 2019-06-20 21:06:26 -06:00
tangxifan cf82d87e11 Merge branch 'multimode_clb' into tileable_routing 2019-06-20 18:18:20 -06:00
tangxifan baab9c4a21 basically finished the coding of tileable rr_graph generator. testing to go 2019-06-20 18:17:07 -06:00
Baudouin Chauviere be25b6dd66 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-20 14:11:03 -06:00
Baudouin Chauviere 3bd6c40a10 Report timing modified to have only one liners 2019-06-20 14:10:39 -06:00
AurelienUoU a7502bb43b Avoid configuration bits for module wihch don't require them 2019-06-20 09:40:41 -06:00
tangxifan e7f2bd3b7c Merge branch 'multimode_clb' into tileable_routing 2019-06-19 21:31:54 -06:00
tangxifan 2f15d2d13c keep developing tileable rr_graph, track2ipin and opin2track to go 2019-06-19 21:30:16 -06:00
AurelienUoU ff00e4c79c Free only if it's possible to free 2019-06-19 16:15:30 -06:00
tangxifan ba15358564 developing ipin2track mapping for tiles 2019-06-18 18:06:21 -06:00
tangxifan 9ca1b42f4c developing switch block pattern for tileable routing architecture 2019-06-18 16:52:42 -06:00
tangxifan 352c97302b start building object GSB graph 2019-06-17 22:10:30 -06:00
tangxifan f4191315da use rr_gsb to build edges of rr_graph 2019-06-17 18:01:45 -06:00
tangxifan 51ff150a77 bug fixing in tileable rr_graph generator 2019-06-17 10:16:08 -06:00
tangxifan 0d14fef53e bug fixing in setting CHANX and CHANY nodes in tileable rr_graph generator 2019-06-16 23:02:18 -06:00
tangxifan 04ffb99ca6 Merge branch 'multimode_clb' into tileable_routing 2019-06-16 16:01:30 -06:00
Baudouin Chauviere 57a4ad1f99 Break memories even in the clb sdc 2019-06-16 14:27:29 -06:00
tangxifan 1af3b5ef55 set chan_rr_nodes in tileable rr_graph builder 2019-06-16 14:23:19 -06:00
tangxifan 8c9cc003ea developing routing track rr_node set up in tileable routing architecture 2019-06-15 18:11:08 -06:00
Xifan Tang 155c8d4924 fix CMakeList bug in disabling VPR graphics 2019-06-15 13:21:25 -06:00
tangxifan d19b470b33 Merge branch 'tileable_routing' into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/regression_verilog.sh
 2019-06-15 12:25:30 -06:00
tangxifan c8bf456097 bug fixing for memory leaking in allocating pb_rr_graph and power estimation 2019-06-15 12:23:36 -06:00
tangxifan d3296d0975 developing tileable rr_graph builder 2019-06-14 22:35:42 -06:00
tangxifan a33627606e developing tileable routing track arrangement 2019-06-14 17:35:40 -06:00
AurelienUoU 29dadc51b4 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-06-14 11:46:02 -06:00
AurelienUoU c76dbaac33 Update regression test avoiding overwritting files 2019-06-14 11:44:44 -06:00
tangxifan 4d2a3680be support bus explicit port mapping to standard cells (for BRAMs) 2019-06-14 11:09:15 -06:00
tangxifan 0902d1e75a c++ string is not working, use char which is stable 2019-06-13 18:38:46 -06:00
tangxifan 5f61cd8876 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 
Conflicts:
	vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
 2019-06-13 16:32:39 -06:00
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
tangxifan dddbbac85c merge from multimode_clb bug fixing 2019-06-13 15:59:34 -06:00
AurelienUoU 15b4cc9ecb Error correction in memory generation for pb_types without modes 2019-06-13 15:34:25 -06:00
tangxifan 43128ad3f0 fix a bug in formal verification port for memory bank configuration circuits 2019-06-13 15:33:13 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan 5ae4dec0af fix bugs in CMakeList on enable/disable VPR Graphics 2019-06-12 22:48:00 -06:00
tangxifan 1d00e3665b start developing tileable_rr_graph_builder 2019-06-11 16:50:40 -06:00
tangxifan 65b5454f3a start developing tileable_rr_graph_builder 2019-06-11 16:49:10 -06:00
AurelienUoU bf13c1f731 Add a script to create a new file with correct path rather than overwrite the existing 2019-06-11 14:28:58 -06:00
Ganesh Gore 1da363f7f1 Merge remote-tracking branch 'lnis_open_fpga/fpga_spice' into ganesh_dev 2019-06-11 11:59:54 -06:00
tangxifan 7245917b9c fix a bug for iopad SPICE generation 2019-06-11 11:43:56 -06:00
Ganesh Gore 1093e341a8 Added additional architecure files 2019-06-11 11:26:44 -06:00
tangxifan 1776ae3ec8 add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
tangxifan 8e3ad675e0 use sstream for rr_block verilog writer 2019-06-10 16:23:35 -06:00
tangxifan 009e5244d3 minor fix on the port direction of configuration peripherals for memory decoders 2019-06-10 15:39:35 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
tangxifan e4f70771a2 updated SDC generator to embrace the RRGSB data structure 2019-06-10 14:47:27 -06:00
tangxifan 8a8f4153ce use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB 2019-06-10 12:50:10 -06:00
tangxifan e31407f693 start cleaning up SDC generator with new RRGSB data structure 2019-06-10 10:57:26 -06:00
tangxifan 17bc7fc296 update Verilog generator to use GSB data structure. SDC generator and TCL generator to go 2019-06-08 20:11:22 -06:00
Xifan Tang 61e359efc5 Enable an option to disable/enable graphics in VPR compilation 2019-06-08 15:08:17 -06:00
tangxifan 90696def6d remove vpr Makefile 2019-06-07 23:44:39 -06:00
tangxifan d737c4ff46 fix path in regression test! TODO: must keep a duplicated copy for template.xml 2019-06-07 23:31:42 -06:00
tangxifan f5b6ee6adf update travis configuration and clean up repository 2019-06-07 22:19:11 -06:00
tangxifan 8c5ec4572d revert string to sprintf 2019-06-07 20:20:41 -06:00