Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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tangxifan
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3f45e6cc87
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remove dead codes for essential gates code generation
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2019-08-22 10:01:52 -06:00 |
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tangxifan
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43de2d7636
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some tuning on Verilog port formatting
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2019-08-21 23:47:50 -06:00 |
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tangxifan
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1be5632e92
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minor tuning on the delay assignment
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2019-08-21 23:11:54 -06:00 |
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tangxifan
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7b0c55ce15
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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
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2019-08-21 22:45:48 -06:00 |
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tangxifan
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5a40c6713d
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managed to plug in refactored essential gates, dead codes to be removed
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2019-08-21 21:50:26 -06:00 |
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tangxifan
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d8eb9866a0
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refactored gate verilog generation
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2019-08-21 18:49:48 -06:00 |
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tangxifan
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b08ff465c9
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refactored pass-gate verilog generation
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2019-08-21 17:33:16 -06:00 |
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tangxifan
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5e156dc725
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minor fix for OSX and update travis using ccache to speed up compilation
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2019-08-21 15:25:36 -06:00 |
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tangxifan
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9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
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a40e5c91ca
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refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
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19472ace4e
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renaming files
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2019-08-20 21:01:38 -06:00 |
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tangxifan
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59f1ac7310
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add missing files and try to refactor submodule essential
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2019-08-20 20:49:26 -06:00 |
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tangxifan
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5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
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60e8d2b29f
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add missing files and try to refactor submodule essential
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2019-08-20 16:13:08 -06:00 |
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tangxifan
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29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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a7ac1e4980
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remame methods in circuit_library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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69039aa742
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developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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bee070d7cc
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start plug in MUX library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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893683fa95
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start developing mux library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
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153d506abb
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add graph-based mux decoding function
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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dcca9f4f0f
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finish mux graph builders
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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638969c3c9
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adding mux graph data structures
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2019-08-20 15:24:52 -06:00 |
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tangxifan
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0b8473e960
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start developing graphs for muxes, with aims to simplify netlist and bitstream generation
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2019-08-20 15:24:52 -06:00 |
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Ganesh Gore
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69ffc38645
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-19 21:59:06 -06:00 |
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Ganesh Gore
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7bfc48b8e4
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Moved spice and verilog netlist folder location
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2019-08-17 01:49:49 -06:00 |
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tangxifan
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aa7f3bef7f
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fixed bugs in configure pb_rr_graph and dependence on testbenches
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2019-08-16 18:20:30 -06:00 |
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tangxifan
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e456b6f905
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replace spice_models with circuit model in bitstream generator
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2019-08-16 16:36:49 -06:00 |
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tangxifan
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5ece7ab6d0
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start refactoring the bitstream part using spice_models
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2019-08-16 15:58:14 -06:00 |
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tangxifan
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b66e120366
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patch on local encoders for unused configuration, avoid chip-burn issues
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2019-08-16 15:32:23 -06:00 |
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tangxifan
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4eb046760b
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still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
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2019-08-15 21:57:59 -06:00 |
AurelienUoU
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8e38aa6019
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Merge with heterogeneous for unfracturable LUT bug fix
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2019-08-14 10:10:27 -06:00 |
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AurelienUoU
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df873903f8
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Bug fix for non fracturable LUT
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2019-08-14 09:32:15 -06:00 |
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AurelienUoU
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30c0f2b6b7
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-14 09:11:54 -06:00 |
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AurelienUoU
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90aaed6e1f
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Fix regression test
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2019-08-14 09:10:13 -06:00 |
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tangxifan
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d2d8af5416
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bug fixing for pb_type num_conf_bits and num_iopads stats
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2019-08-13 17:34:09 -06:00 |
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tangxifan
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edfa72a666
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try to fix the bug in clock net identification
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2019-08-13 16:47:28 -06:00 |
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tangxifan
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1118b28397
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use single subckt for switch box again, to abolish the multi-module subckt
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2019-08-13 16:11:04 -06:00 |
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tangxifan
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4cffd8ac2d
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keep route file updated with tileable rr_graph
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2019-08-13 15:37:42 -06:00 |
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tangxifan
|
c7526cb43c
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memory sanitized
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2019-08-13 14:19:40 -06:00 |
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tangxifan
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ef4d15df4e
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reorganize the libarchfpga repository
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2019-08-13 13:37:35 -06:00 |
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tangxifan
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392f579836
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add linking functions for circuit models and architecture, memory sanitizing is ongoing
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2019-08-13 13:25:23 -06:00 |
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AurelienUoU
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8dab4dec90
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-08-13 11:09:29 -06:00 |
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AurelienUoU
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7851246424
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Resolve merge issue
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2019-08-13 11:08:30 -06:00 |
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tangxifan
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c56f289d3e
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add checkers for circuit library
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2019-08-12 16:45:33 -06:00 |