Commit Graph

517 Commits

Author SHA1 Message Date
tangxifan b469705819
Merge branch 'master' into fpga_sdc_test 2021-04-11 21:14:46 -06:00
tangxifan 94c4c817eb [Test] Expand sdc time unit test to sweep all the available units 2021-04-11 20:14:09 -06:00
tangxifan a4893e27cf [Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification 2021-04-11 17:26:27 -06:00
tangxifan 44d97ead86
Merge branch 'master' into hetergeneous_arch 2021-03-23 17:05:03 -06:00
tangxifan 8c970a792a [Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier 2021-03-23 15:33:00 -06:00
tangxifan 351dec5935 [Test] Add QoR csv file for vtr benchmarks 2021-03-23 11:15:02 -06:00
tangxifan 61eddb08de [Test] Update task configuration by commenting out high-runtime VTR benchmarks 2021-03-22 14:42:42 -06:00
tangxifan 4bfd0c0a02 [Test] Enable more VTR benchmark in testing 2021-03-22 12:53:30 -06:00
tangxifan cc10b10703 [Test] Enable more benchmarks for testing; See problems when mapping BRAMs 2021-03-20 22:53:37 -06:00
tangxifan 9a3aff274f [Test] Use fix routing channel width to save runtime for VTR benchmarks 2021-03-20 21:59:44 -06:00
tangxifan ca9a70fc88 [Test] Comment out benchmarks have problems in synthesis 2021-03-20 21:29:21 -06:00
tangxifan 125e94a6b3 [Test] Add full VTR benchmark (with most commented); ready for massive testing 2021-03-20 21:01:18 -06:00
tangxifan f3792bc6f6 [Test] Update VTR benchmark test case to include DSP example benchmark 2021-03-20 18:09:19 -06:00
tangxifan 1976a8068f [Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added) 2021-03-17 15:11:17 -06:00
tangxifan e1f8b252b1 Merge branch 'master' into yosys_heterogeneous_block_support 2021-03-16 20:05:21 -06:00
tangxifan d12a8a03fd [Test] Update test case using yosys bram parameters 2021-03-16 19:52:17 -06:00
tangxifan 73b06256d0 [Test] Deploy the new yosys script supporting BRAM to regression tests 2021-03-16 16:52:59 -06:00
tangxifan e61857aa2b
Merge branch 'master' into ganesh_dev 2021-03-11 19:17:02 -07:00
tangxifan 366bec232c [Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI 2021-03-11 15:25:48 -07:00
tangxifan a6186db315 [Test] Update bitstream annotation with new syntax 2021-03-10 20:45:17 -07:00
tangxifan 7d07f5d8cb [Test] Update bitstream setting example with mode bit overwriting 2021-03-10 15:34:53 -07:00
tangxifan d21909ad6c [Test] Use custom rewriting script in lut_adder test 2021-03-10 13:48:20 -07:00
Tarachand Pagarani db8ea86b2f update tests to use no_ff_map and remove tests that need async set/reset for now 2021-03-10 10:04:45 -08:00
Tarachand Pagarani 608bd1f658 comment out desings that utilize local async reset/preset 2021-03-09 19:24:01 -08:00
Tarachand Pagarani 7f4c20ff33 comment out desings that utilize local async reset/preset 2021-03-09 10:37:06 -08:00
Tarachand Pagarani c4b83aeaa9 bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type 2021-03-09 00:46:40 -08:00
tangxifan 37aa42d305 [Test] Patch task configuration file for lut_adder_test to use correct rewrite script 2021-03-08 21:38:51 -07:00
Lalit Sharma 7945628307 Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification 2021-03-07 22:25:01 -08:00
Lalit Sharma 6a1ce01084 Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS 2021-03-07 22:02:11 -08:00
Lalit Sharma 0cbad747a1 Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family 2021-03-04 01:10:47 -08:00
Lalit Sharma 817729ac86 Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables 2021-03-01 22:31:15 -08:00
tangxifan e34380a654
Merge branch 'master' into default_net_type 2021-03-01 08:38:58 -07:00
Lalit Sharma ea4aee8cb2 For time-being yosys script running in no_adder mode. 2021-02-28 22:07:23 -08:00
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
tangxifan 9f4d05da67 [Test] Bug fix for new test case 2021-02-28 16:11:30 -07:00
tangxifan 18a7041424 [Test] Add default net type test for explicit port mapping 2021-02-28 12:31:32 -07:00
tangxifan ff29cc3dff [Test] Move tests to a test group 2021-02-28 12:23:35 -07:00
tangxifan 9cb1ca42fe [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
tangxifan 0d82e4939c [Test] Use unified quicklogic synthesis script and enable end-of-flow tests 2021-02-26 09:35:40 -07:00
tangxifan 870d3a0e27 Merge branch 'master' into dev 2021-02-26 09:28:42 -07:00
Lalit Sharma 1082d3c677 Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys 2021-02-25 23:39:07 -08:00
Lalit Sharma 1e48d4f6dc Modifying custom yosys script file name 2021-02-25 22:21:39 -08:00
tangxifan a62786986b [Test] Turn off verification in adder lut test temporarily 2021-02-23 19:03:25 -07:00
tangxifan 53df7f69e7 [Test] Bug fix in the test case using lut adder 2021-02-23 16:59:46 -07:00
tangxifan db71cc8a16 [Test] Add LUT adder test using quicklogic synthesis script 2021-02-23 16:50:58 -07:00
tangxifan 19f6b221b1 [Test] Rework comments on runtime 2021-02-22 15:25:57 -07:00
tangxifan 4803b0ce42 [Test] Add test case for sdc controller 2021-02-22 15:02:14 -07:00
tangxifan 2e2b1cb6e7 [Test] Use hetergenenous FPGA architecture in quicklogic tests 2021-02-22 13:41:04 -07:00
tangxifan bc30f62c5a [Test] Add test for sdc controller 2021-02-22 12:41:53 -07:00
tangxifan 60dc194d8f [Test] Bug fix in the 5clock test case 2021-02-22 11:46:23 -07:00
tangxifan 71e0026a50 [Test] Add new test for 5-clock counter to quicklogic tests 2021-02-22 11:32:17 -07:00
tangxifan bc8aa0ebc6 [Test] Remove routing test from quicklogic's flow test 2021-02-22 10:22:47 -07:00
tangxifan 9b6b2068ee [Test] Move MCNC test to benchmark sweep test group 2021-02-22 10:18:34 -07:00
tangxifan c1f4a434e4 [Doc] Update README for the regression test tasks 2021-02-22 10:17:02 -07:00
Lalit Narain Sharma be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
Lalit Sharma 576e6753f6 Removing 2 more tests which are variant of and design 2021-02-19 09:11:19 -08:00
Lalit Sharma 6de0954ca5 Uncommenting all benchmarks except 2 that requires multiple clocks 2021-02-19 08:40:26 -08:00
tangxifan e19fc15fec [Test] bug fix in test case 2021-02-18 19:37:45 -07:00
tangxifan 2e88b035ed [Test] Add wire LUT repacker test case 2021-02-18 19:37:44 -07:00
Lalit Sharma 69cdc11ea5 Uncommenting the tests that are running fine 2021-02-18 04:17:12 -08:00
tangxifan d85d6e964e
Merge pull request #227 from watcag/master
Standard-cell flow
2021-02-17 10:11:34 -07:00
Lalit Sharma 44a979288b Adding quicklogic tests and updating the corresponding conf file to run them 2021-02-16 23:08:38 -08:00
Tarachand Pagarani 426b6449d8 change the test to turn off power analysis 2021-02-15 02:45:38 -08:00
tangxifan 3ae501a5ea [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
tangxifan 2b51b36dd6 [Test] Now use the super LUT arch in the test case 2021-02-09 15:27:44 -07:00
tangxifan 56284059de [Test] Add a test case for a super LUT 2021-02-09 15:25:32 -07:00
Nachiket Kapre 6bb2e29f17 default to ns for time unit -- synopsys dc whines 2021-02-09 17:04:52 -05:00
Nachiket Kapre 87c69460df what is going on 2021-02-09 11:33:08 -05:00
Nachiket Kapre cc74c6268a trying fix chan width 2021-02-09 11:28:19 -05:00
Nachiket Kapre b14b5f975d adding sweep for W 2021-02-09 08:48:25 -05:00
Nachiket Kapre d040ba569c merge for consideration; 2021-02-08 21:29:34 -05:00
Nachiket Kapre 94f858fcde merge for consideration; 2021-02-08 21:27:01 -05:00
tangxifan 8853370c60 [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
tangxifan 31441c0b64 [Test] Deploy adder_8 to soft adder test 2021-02-03 09:26:38 -07:00
tangxifan 8e36ed1ab6 [Test] Update task configuration to use and2 eblif 2021-02-02 15:01:15 -07:00
tangxifan 5e2847bc41 [Test] Update test case to use eblif file 2021-02-02 09:33:41 -07:00
tangxifan 9ff5e7926b [Test] Update test case to use the adder benchmark 2021-02-02 09:24:39 -07:00
tangxifan 04594cb7ab [Test] Adapt bitstream annotatin file to parser's requirement 2021-02-01 17:38:36 -07:00
tangxifan 280c9620aa [Test] Add an example bitstream annotation file 2021-02-01 16:01:21 -07:00
tangxifan 940dce469a [Test] Bug fix for test case configuration 2021-02-01 11:19:47 -07:00
tangxifan a80acfb547 [Test] Add new test case to CI script 2021-02-01 11:16:12 -07:00
tangxifan af630dab1e [Test] Add soft adder test case. This is placeholder. Test arch will be elaborated 2021-02-01 10:53:38 -07:00
tangxifan 9cce411eda [Test] Add adder test cases 2021-02-01 10:42:24 -07:00
AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200)
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
tangxifan af0646260c [Test] Bug fix in pin constraints 2021-01-19 17:44:05 -07:00
tangxifan 186f2f1968 [Test] Use pin constraint in multi-clock test case 2021-01-19 17:42:40 -07:00
tangxifan e17a5cbbf2 [Test] Rename to pin constraint to comply with libpcf requirement 2021-01-19 15:52:51 -07:00
tangxifan ab25e1af5f [Test] Add example XML for net mapping between benchmark to FPGA 2021-01-19 09:29:21 -07:00
tangxifan ea9d6bfe91 [Flow] Update the design constraint file to follow bug fix in parser 2021-01-17 10:41:01 -07:00
tangxifan dd74f05a31 [Test] Add repack constraints to tests 2021-01-17 10:35:36 -07:00
tangxifan d0e05b3575 [Lib] Now use pb_type in design constraints instead of physical tiles 2021-01-16 21:35:43 -07:00
tangxifan 8578c1ecac [Flow] Rename the design contraint file syntax 2021-01-16 15:35:13 -07:00
tangxifan 9154cfdeec [Flow] Add comments for the design constraint file 2021-01-16 15:34:01 -07:00
tangxifan 6ab0f71896 [Test] Add an example of repack pin constraints file 2021-01-16 14:38:39 -07:00
tangxifan 3b5394b45f [Test] Now use dedicated simulation settings for the 4-clock architecture 2021-01-14 15:40:16 -07:00
tangxifan 314e458632 [Test] Update task configuration to use post-yosys .v file in verification 2021-01-13 15:42:45 -07:00
tangxifan 91f12071d5 [Test] Use counter4bit in the multi-clock test 2021-01-13 13:34:59 -07:00
tangxifan 250adb01cf [Test] Update test case to use blif_vpr flow with detailed explaination on the choice 2021-01-13 13:18:31 -07:00
tangxifan 99e2a068fb [Test] Add a test case for multi-clock 2021-01-12 18:06:25 -07:00
tangxifan e58e1e86c2 [Test] Update test case to use new shell script 2021-01-10 11:09:10 -07:00
tangxifan 1c68e43acf [Test] Add new test case for registerable I/O architecture 2021-01-10 11:00:21 -07:00
tangxifan 43418cd76b [Test] Deploy pipeplined and2 to test cases 2021-01-10 10:28:22 -07:00
tangxifan 06af30ef10 [Test] Add test case for the SCFF usage in configuration chain 2021-01-04 17:30:19 -07:00
Lalit Sharma 2484721a45 Updating write_verilog_testbench by removing option explicit_port_mapping 2020-12-22 22:17:50 -08:00
Lalit Sharma 3c9e4919b4 Updating variable name in ys to call BLIF output file. 2020-12-18 03:18:46 -08:00
Lalit Sharma 891e2f8aa3 Adding arch xml from SOFA repo. Also updating the script with its file location 2020-12-16 04:14:18 -08:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
tangxifan 0cb8457e21 [Test] Add test case for tileable I/O 2020-12-04 16:02:47 -07:00
tangxifan 179b0ce304 [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00
tangxifan 27a480b5f8 [Test] arch name fix in the test case 2020-11-30 17:45:54 -07:00
tangxifan a1d3b439d3 [Test] Add a new test case to define a global reset port from a global tile port 2020-11-30 17:19:12 -07:00
ganeshgore 7db030018c [Bug] Fixed variable file location 2020-11-25 22:44:40 -07:00
tangxifan b8559249dc [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
tangxifan 26e4db56ad [Test] Add new test case for the native fracturable LUT4 2020-11-25 22:21:23 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1d993296d8 [Flow] Example of using test variable in task conf 2020-11-25 17:25:12 -07:00
tangxifan 617f7e3062 [Flow] disable signal initialization for behavioral verilog generation 2020-11-22 21:13:22 -07:00
tangxifan 655da9f3d0 [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
tangxifan 845436fa71 [Test] Add sequential benchmark for global tile clock test case 2020-11-17 14:34:54 -07:00
tangxifan 485258a9ea [Test] Add test case for global clock from tiles 2020-11-10 19:24:25 -07:00
tangxifan 6b48ee7f0b [Test] Add new test for caravel io support 2020-11-04 20:58:40 -07:00
tangxifan 61376a2979 [Test] Add test cases for various tile organization 2020-11-04 16:32:52 -07:00
tangxifan 65ca53ac98 [Test] Update test case with the new arch name 2020-11-02 13:16:42 -07:00
tangxifan bc00dee858 [Test] Add test case for embedded I/O 2020-11-02 12:28:25 -07:00
tangxifan 4c14428400 [Test] Add test case for fast configuration support on multi-region frame-based configuration protocol 2020-10-30 10:50:00 -06:00
tangxifan ca7d43275d [Test] Add test case for multi_region configuration frame 2020-10-30 10:48:29 -06:00
tangxifan 241ebf054a [Test] Add a test case for validating fast configuration techniques on multi-region memory banks 2020-10-29 16:29:46 -06:00
tangxifan ff386001c4 [Test] Add openfpga task for multi-region memory banks 2020-10-29 13:56:32 -06:00
tangxifan 179ae355d0 [Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops 2020-10-13 12:02:26 -06:00
tangxifan 97c3bf7ea0 [Test] Add a test case for non-constant input multiplexers 2020-10-13 11:58:17 -06:00
tangxifan 570b494df7 [Test] Add test case for using GND signal as constant input for routing multiplexers 2020-10-13 11:38:54 -06:00
tangxifan dc68c52d0a [Test] Now use a light architecture to speed up the test case runtime 2020-10-12 12:53:34 -06:00
tangxifan 8941e38613 [Test] Enable verification in the new test case 2020-10-12 12:50:08 -06:00
tangxifan 9e1fd300dc [Test] Add test case for customized location of fabric netlists 2020-10-12 12:47:58 -06:00
tangxifan 82e7b159ce [Regression test] Add test case for fracturable LUT using AND gate to switch modes 2020-10-10 20:26:41 -06:00
tangxifan d4d02ab16a [Regression Test] Move fabric key tests to basic tests 2020-09-29 14:22:23 -06:00
tangxifan ff6570df9d [Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI 2020-09-29 14:19:40 -06:00
tangxifan 02ea639959 [Regression Test] Add test for fabric key based on multiple region 2020-09-29 14:13:38 -06:00
tangxifan a0d1d68402 [Regression Test] Add regression tests for smart fast configuration chain using multiple regions 2020-09-29 13:53:41 -06:00
tangxifan 5be5835b71 [Regression Test] Add multiple region configuration chain test case 2020-09-29 13:48:39 -06:00
tangxifan 19dd3778d9 [Architecture] Add test case for memory bank to use both reset and set 2020-09-24 17:04:24 -06:00
tangxifan 335f5b78c1 [Regression Test] Add test case to use both set and reset for configuration frame 2020-09-24 17:02:28 -06:00
tangxifan 2d81ff9012 [Regression test] Add configuration chain test case where both set and reset are used 2020-09-24 16:59:52 -06:00
tangxifan 7fbccdd102 [Regression Tests] Add test cases for configuration chain using different DFF cells 2020-09-24 14:34:12 -06:00
tangxifan efad0402c2 [Regression Test] Bug fix for CI errors 2020-09-24 13:55:41 -06:00
tangxifan e7906899dd [Regression test] Bug fix for fast configuration frame. Now should use a latch with reset 2020-09-24 13:53:12 -06:00
tangxifan ffd1a72d22 [Architecture] Add regression tests for the frame-based configuration using reset and set signals 2020-09-24 12:18:26 -06:00
tangxifan fde15c4f88 [Regression Test] Add test for fast memory bank configuration using set signals 2020-09-24 12:13:35 -06:00
tangxifan 48083d2276 [Regression Test] Adapt fast memory bank test case 2020-09-24 10:32:03 -06:00
tangxifan 186f00edfc [Regression Test] Add test cases for memory bank using different SRAM cells 2020-09-24 10:25:03 -06:00
tangxifan 5b0d451f0f [Regression Test] Add test case for configurable latch with active-low set 2020-09-23 23:04:10 -06:00
tangxifan 8e780635df [Regression Test] Rename test case in CI 2020-09-23 22:59:46 -06:00
tangxifan d0cef68242 [Regression test] Add test case for using resetb 2020-09-23 22:58:59 -06:00
tangxifan 73e59d67af [Architecture] Add test case for fast configuration using set signals 2020-09-23 21:50:23 -06:00
tangxifan 349aa79069 [Regression test] Add test case for smart fast configuration 2020-09-23 21:49:38 -06:00
tangxifan 05c2e652a4 [Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol 2020-09-23 20:44:06 -06:00
tangxifan 906191e931 [Architecture] Use strict latch Verilog HDL in frame-based procotol 2020-09-23 17:58:13 -06:00
tangxifan ad385c6d69 [Regression Test] Add test case for using SRAM cell in frame-based configuration 2020-09-23 17:39:36 -06:00
tangxifan f23c25e123 [Regression Test] Add test case for configurable latch with active-low reset 2020-09-23 17:25:17 -06:00
tangxifan 149d5b20bd [Regression Test] Add test case for fixed device support 2020-09-23 16:47:11 -06:00
tangxifan 3350695806 [Regression test] Add test case for pattern based local routing architecture 2020-09-23 16:06:47 -06:00
tangxifan 7729f671ab [Regression Tests] Remove deadlink 2020-09-22 18:35:41 -06:00
tangxifan 51c0319657 [Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:54 -06:00
tangxifan 3d1f49fb2f [Regression Test] Add testcase for k4n4 with multiple segments 2020-09-22 12:47:41 -06:00
tangxifan 5741664580 [Regression Test] Add test case for k4n4 bram architecture 2020-09-22 12:23:56 -06:00
tangxifan 3bf94b8e34 [Regression test] Remove no local routing from fpga verilog tests 2020-09-22 11:48:19 -06:00
tangxifan 7ed9f76b06 [Regression test] Move k4n4 no local routing to basic test 2020-09-22 11:47:03 -06:00
tangxifan 2dea97afb6 [Regression test] reduce runtime for k4n4 test in basic testing 2020-09-22 11:45:29 -06:00
tangxifan ea4dd410b7 [Regression Test] Add k4n4 fracturable lut test case to basic test 2020-09-22 11:41:36 -06:00
tangxifan dad19cac9a [Regression test] Add k4 series architecture: fracturable adder 2020-09-22 11:39:18 -06:00
tangxifan acf318f184 [Regression test] Bug fix in test case fabric_chain 2020-09-21 18:58:35 -06:00
tangxifan e4291eb27e [Regression Tests] Now use fixed device layout in test cases for best coverage 2020-09-21 18:44:13 -06:00
tangxifan a83bc3f75c [Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI 2020-09-21 17:38:16 -06:00
tangxifan 681e80d4b6 [Regression tests] update frac_lut test case using more representative benchmarks 2020-09-17 10:39:22 -06:00
tangxifan c40c9f5876 [Regression test] add test case for no local routing architecture 2020-09-16 18:05:33 -06:00
tangxifan 35d47ee0e7 [Regression tests] bug fix in the test case for fully connected output crossbar 2020-09-16 17:33:54 -06:00
tangxifan 30fb99095f [Regression Tests] Add new test case for fully connected output crossbar 2020-09-16 17:29:15 -06:00
tangxifan f42411c29e [Regression Tests] Add test cases for routing multiplexer design with input/output buffers only 2020-09-14 16:03:43 -06:00
tangxifan 9bf0e772a3 [Regression Tests]Add a new testcase for routing multiplexer designs without buffers 2020-09-14 15:45:35 -06:00
tangxifan 6c925dcded [regression test] Add more tests for thru channels and deploy to CI 2020-08-19 20:11:37 -06:00
tangxifan bf08e1841c add new test case using thru channels 2020-08-19 17:58:34 -06:00
tangxifan cadf29022e add README to explain the organization of regression tests 2020-07-28 13:44:06 -06:00
tangxifan f33422d4d7 add regression test to track runtime on big fpga devices using practical benchmarks 2020-07-28 12:38:42 -06:00
tangxifan a156807559 enrich basic regression tests to cover more critical microbenchmarks 2020-07-27 19:47:43 -06:00
tangxifan 5d83abb2cf bug fix in read architecture bitstream and regression tests 2020-07-27 19:37:05 -06:00
tangxifan 50cc4dfba3 classify regression test to dedicated categories 2020-07-27 17:18:59 -06:00
tangxifan 5595ee9052 refine the test case for load external arch bitstream 2020-07-27 16:53:29 -06:00
tangxifan cec6bf0b6f add or2 microbenchmark for testing external arch bitstream 2020-07-27 15:59:03 -06:00
tangxifan 4174fbf77d add load architecture bitstream test case and reorganize regression tests in category of openfpga tools 2020-07-27 15:54:46 -06:00
tangxifan a3eba8acbe update task files using the new syntax on SHELL variables 2020-07-27 15:25:49 -06:00
tangxifan c87f6b75b9 add test case for FPGA-SPICE 2020-07-24 19:12:35 -06:00
tangxifan 020154b0cd add depopulate crossbar test case 2020-07-24 18:06:02 -06:00
tangxifan ca867ea6fa add power gate inverter test case (full testbench) 2020-07-22 20:09:52 -06:00
tangxifan 1a1c3885e7 use k6 n10 in mux designs to speed up CI 2020-07-22 13:54:09 -06:00
tangxifan 95c1fe61e1 use k6 n8 in mux design to speed up CI 2020-07-22 13:49:03 -06:00
tangxifan f754c8af06 use k6_n10 architecture to reduce CI runtime 2020-07-22 13:45:55 -06:00
tangxifan 92c3449999 bug fix in the regression test due to benchmark changes 2020-07-22 13:17:05 -06:00
tangxifan 05dccadf21 bug fix in the testcases using yosys_vpr flow 2020-07-22 12:44:19 -06:00
tangxifan 1d36de817f adapt generate bitstream testcase to use yosys vpr flow 2020-07-22 12:24:34 -06:00
tangxifan b96cdbf857 adapt preconfig test cases to use yosys_vpr flow 2020-07-22 12:23:39 -06:00
tangxifan d8804f4ec1 deploy yosys_vpr flow to basic regression tests 2020-07-22 12:21:59 -06:00
tangxifan eb070694b5 fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture 2020-07-15 17:52:41 -06:00
tangxifan ca90f337a7 add fast configuration chain test case 2020-07-15 11:56:47 -06:00
tangxifan 1e6955aaa4 rename arch directory to be clear for its usage 2020-07-04 19:13:28 -06:00
tangxifan f9a2bb0490 Reorganize task directory 2020-07-04 19:06:41 -06:00
tangxifan 4f8260a7ba remove obselete codes and update regression tests 2020-07-04 17:31:34 -06:00
tangxifan 1c634e4600 add missing task file for generate bitstream test case 2020-07-02 17:24:51 -06:00
tangxifan 0d81f60fd8 add new options to openfpga task configuration files 2020-06-12 19:48:39 -06:00
ganeshgore 559564c333 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2020-06-12 17:31:14 -06:00
tangxifan 2d35848cfa add external key test cases 2020-06-12 13:11:21 -06:00
tangxifan 65b387a589 develop test cases for fabric keys 2020-06-12 11:32:52 -06:00
tangxifan 068d9943e7 update all the templates and regression test cases with simulation settings 2020-06-11 19:31:16 -06:00
tangxifan 1842bf51e1 deploy read_openfpga_simulation_setting in CI on a single test case 2020-06-11 19:31:16 -06:00
tangxifan c87dbc4880 start using counter benchmark in regression tests 2020-06-11 19:31:15 -06:00
tangxifan 3f9afea3e8 add preconfig testbench test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 288294c23a add fast configuration test case for memory bank configuration protocol 2020-06-11 19:31:14 -06:00
tangxifan 73d4c835b7 add regression test case for memory bank 2020-06-11 19:31:13 -06:00
tangxifan 2def059b5b add standalone configuration protocol to pre config test cases 2020-06-11 19:31:12 -06:00
tangxifan 5f6a790eff add new test cases for the standalone memory configuration protocol 2020-06-11 19:31:12 -06:00
tangxifan a5138113e4 add fast configuration testcase 2020-06-11 19:31:12 -06:00
tangxifan 8b3e79766c add fast configuration option to fpga_verilog to speed up full testbench simulation 2020-06-11 19:31:12 -06:00
tangxifan 05aa166a9e add preconfig testbench cases to regression tests for different configuration protocols 2020-06-11 19:31:11 -06:00
tangxifan 827e2e6713 file moving in regression tests 2020-06-11 19:31:11 -06:00
tangxifan 1e73fd6def create configuration frame example script 2020-06-11 19:31:10 -06:00
tangxifan 3a0d3b4e95 fix the broken CI/regression tests due to incorrect file path 2020-06-11 19:31:10 -06:00
tangxifan 3fa3b17061 start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches. 2020-06-11 19:31:10 -06:00
tangxifan fc2b09514e add configuration chain write to regression tests 2020-06-11 19:31:06 -06:00
tangxifan 98fbcb5410 add time unit test for SDC generation to CI 2020-06-11 19:31:04 -06:00
tangxifan 4083fae41a add new test cases about user-defined simulation settings 2020-06-11 19:31:03 -06:00
tangxifan 889bc8dbe8 add more test cases about LUT design and deploy to CI 2020-06-11 19:31:02 -06:00
tangxifan 889f179ce7 add local encoder test case 2020-06-11 19:31:01 -06:00
tangxifan 98a658a013 bug fixed in routing_test.v. Deployed to regression tests 2020-06-11 19:31:01 -06:00
tangxifan 6dd8d347e1 try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif 2020-06-11 19:31:01 -06:00
tangxifan 42cede37fa add testcases on generate fabric/testbench only 2020-06-11 19:31:01 -06:00
tangxifan 9bf91bd92a start testing mcnc_big20 using OpenFPGA tasks 2020-06-11 19:30:55 -06:00
ganeshgore c31b20dc91 Added support for simulation setting file in the task flow 2020-06-11 19:28:13 -06:00
ganeshgore c1b73efa62 Added support for simulation setting file in the task flow 2020-06-10 23:12:30 -06:00
tangxifan 90f608baea changing task mcnc file for debugging (temporarily now) Will be corrected later 2020-04-23 18:58:39 -06:00
tangxifan f9fcc6b471 tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation 2020-04-22 18:24:09 -06:00
tangxifan 726185cd5e add test cases using spypad architecture 2020-04-22 12:56:57 -06:00
tangxifan 9761d13eef update microbenchmark and2 module name 2020-04-20 13:37:39 -06:00
tangxifan 489ca75230 adapt benchmark and_latch module name to be different than benchmark and 2020-04-20 13:15:05 -06:00
tangxifan f6b7583a2a add tasks for single mode 2020-04-20 12:55:40 -06:00
tangxifan 8b03ec900f fine-tune micro benchmark to fit port mapping in testbenches 2020-04-19 17:05:12 -06:00
tangxifan e10cafe0a5 Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
2020-04-19 16:42:31 -06:00
tangxifan 32ed609238 update micro benchmark set and regression tests using them 2020-04-19 12:49:07 -06:00
tangxifan cc163081f5 recover mcnc big20 test configuration 2020-04-18 21:06:43 -06:00
tangxifan 2e3a811f4f critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results 2020-04-18 21:04:46 -06:00
tangxifan f76a3090c4 add mcnc big20 test cases and start debugging 2020-04-18 19:25:16 -06:00