Eddie Hung
63b7a48fbc
clkpart to analyse async flops too
2019-11-25 12:04:11 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Eddie Hung
23ecf12bbf
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:29:03 -08:00
Eddie Hung
15aa3f460d
More oopsies
2019-11-23 10:28:46 -08:00
Eddie Hung
bf1167bc64
Conditioning abc9 on POs not accurate due to cells
2019-11-23 10:26:55 -08:00
Eddie Hung
7b2bccb3d3
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 10:18:06 -08:00
Eddie Hung
722eeacc09
Print ".en=" only if there is an enable signal
2019-11-23 10:17:31 -08:00
Eddie Hung
907c8aeaef
Escape IdStrings
2019-11-23 10:16:56 -08:00
Eddie Hung
165f5cb6cf
More sane naming of submod
2019-11-23 10:01:09 -08:00
Eddie Hung
66ff0511a0
Add -set_attr option, -unpart to take attr name
2019-11-23 09:52:17 -08:00
Eddie Hung
fb49da21bd
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-23 08:39:19 -08:00
Eddie Hung
96941aacbb
Do not use log_signal() for empty SigSpec to prevent "{ }"
2019-11-22 23:29:10 -08:00
Eddie Hung
736b96b186
Call submod once, more meaningful submod names, ignore largest domain
2019-11-22 23:16:15 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
cba3073026
submod to bitty rather bussy, for bussy wires used as input and output
2019-11-22 20:53:58 -08:00
Eddie Hung
900c806d4e
Move clkpart into passes/hierarchy
2019-11-22 17:25:53 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
8119383f81
Constant driven signals are also an input to submodules
2019-11-22 17:23:51 -08:00
Eddie Hung
89a4a4d90f
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:04:33 -08:00
Eddie Hung
573396851a
Oops
2019-11-22 17:03:30 -08:00
Eddie Hung
bf7d36627e
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4
Only action if there is more than one clock domain
2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4
Replace TODO
2019-11-22 16:58:08 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
6a52897aee
sigmap(wire) should inherit port_output status of POs
2019-11-22 16:48:11 -08:00
Eddie Hung
698854955c
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb
Brackets
2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5
Entry in Makefile.inc
2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d
New 'clkpart' to {,un}partition design according to clock/enable
2019-11-22 15:35:51 -08:00
Clifford Wolf
03fb92ed6f
Add "opt_mem" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-22 17:45:22 +01:00
Eddie Hung
c4ec42ac38
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
...
Since they should be captured downwards from the owning flop
2019-11-21 16:17:03 -08:00
David Shah
ca99b1ee8d
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 20:46:41 +00:00
Eddie Hung
729c6b93e8
endomain -> ctrldomain
2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
David Shah
7ff5d6d30a
memory_collect: Copy attr from RTLIL::Memory to cell
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-18 13:58:03 +00:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Clifford Wolf
527434de49
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
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wreduce: Don't trim zeros or sext when not matching ARST_VALUE
2019-11-17 10:42:30 +01:00
David Shah
f5804a84fd
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-14 18:43:15 +00:00
Clifford Wolf
e907ee4fde
Merge pull request #1490 from YosysHQ/clifford/autoname
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Add "autoname" pass and use it in "synth_ice40"
2019-11-14 18:03:44 +01:00
Clifford Wolf
07c854b7af
Add "autoname" pass and use it in "synth_ice40"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-13 13:41:16 +01:00
whitequark
ab0fb19cff
Merge pull request #1488 from whitequark/flowmap-fixes
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flowmap: fix a few crashes
2019-11-13 11:57:17 +00:00
Clifford Wolf
4be5a0fd7c
Update fsm_detect bugfix
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 17:31:30 +01:00
Clifford Wolf
16df8f5a32
Bugfix in fsm_detect
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-12 14:26:02 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
...
Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
...
Fixes #1405 .
2019-11-11 23:13:00 +00:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
...
On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Clifford Wolf
b8774ae849
Fix dffmux peepopt init handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:32 +02:00
Clifford Wolf
bb0851bfc5
Move GENERATE_PATTERN macro to separate utility header
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 11:40:01 +02:00
Clifford Wolf
af61d92441
Disable left-over log_debug in peepopt_dffmux.pmg
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-16 10:43:47 +02:00
Eddie Hung
304e5f9ea4
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-08 13:03:06 -07:00
Eddie Hung
ea54b5ea61
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
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This reverts commit f46ac1df9f
.
2019-10-08 12:41:24 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427
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Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
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async2sync to be called by equiv_opt only when -async2sync given
2019-10-08 10:53:44 -07:00
Eddie Hung
9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
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Rename abc_* names/attributes to more precisely be abc9_*
2019-10-08 10:53:38 -07:00
Eddie Hung
472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
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Add notes and comments for xilinx_dsp
2019-10-08 10:53:30 -07:00
Eddie Hung
2cb2116b4c
Use "abc9_period" attribute for delay target
2019-10-07 15:03:44 -07:00
Clifford Wolf
4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
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Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-06 12:11:20 +02:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
5c68da4150
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
2019-10-05 09:27:12 -07:00
Clifford Wolf
10d0bad67e
Update README.md
2019-10-05 18:13:04 +02:00
Eddie Hung
f90a4b1e24
Missed this
2019-10-05 08:57:37 -07:00
Eddie Hung
991c2ca95b
Add comment on why we have to match for clock-enable/reset muxes
2019-10-05 08:56:37 -07:00
Eddie Hung
ebb059896a
Add note on pattern detector
2019-10-05 08:53:01 -07:00
Miodrag Milanović
7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
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Fixes for MSVC build
2019-10-05 07:48:30 +02:00
Eddie Hung
792cd31052
Add comments for xilinx_dsp_cascade
2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0
Improve comments for xilinx_dsp_CREG
2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6
Fix comment
2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b
Restore optimisation for sigM.empty()
2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a
Retry on fixing TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8
Revert "Fix TODOs"
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This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619
More comments, cleanup
2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931
Fix TODOs
2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e
Consistency
2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478
Add comments for xilinx_dsp
2019-10-04 22:31:04 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8
Fix from merge
2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf
Fix xilinx_dsp for unsigned extensions
2019-10-04 16:46:15 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
84f978bdc2
Add -async2sync to help text as per @daveshah1
2019-10-04 10:17:46 -07:00
Miodrag Milanovic
c0b14cfea7
Fixes for MSVC build
2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Eddie Hung
a9efd2e81c
Restore part of doc
2019-10-03 10:51:53 -07:00
Eddie Hung
7a6dec1cef
Add new -async2sync option
2019-10-03 10:30:51 -07:00
Eddie Hung
8765ec3c27
Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"
...
This reverts commit a39505e329
.
2019-10-03 10:07:15 -07:00
Eddie Hung
c6d15c9aad
Revert "Update doc for equiv_opt"
...
This reverts commit a274b7cc86
.
2019-10-03 10:07:03 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped
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Add "check -mapped"
2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b
Add "check -allow-tbuf"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7
Fix broken CI, check reset even for constants, trim rstmux
2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a
Refactor peepopt_dffmux and be sensitive to \init when trimming
2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f
Be mindful that sigmap(wire) could have dupes when checking \init
2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7
Add "check -mapped"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c
Resolve FIXME on calling proc just once
2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663
Add comment
2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Eddie Hung
a274b7cc86
Update doc for equiv_opt
2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync
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equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880
Fix $dlatch handling in async2sync
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-30 14:58:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9
Fix "scc" call inside abc9 to consider all wires
2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
313d2478e9
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
2019-09-27 18:41:04 -07:00
Eddie Hung
fe722b737c
Add -select option to aigmap
2019-09-27 17:44:01 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Eddie Hung
a39505e329
equiv_opt to call async2sync when not -multiclock like SymbiYosys
2019-09-27 12:59:10 -07:00
Eddie Hung
aebbfffd71
Ooops AREG and BREG to default to -1
2019-09-27 11:57:53 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
26657037b8
Update doc with max cascade chain of 20
2019-09-26 14:31:02 -07:00
Eddie Hung
5b9deef10d
Do not always zero out C (e.g. during cascade breaks)
2019-09-26 13:59:05 -07:00
Eddie Hung
95f0dd57df
Update doc
2019-09-26 13:44:41 -07:00
Eddie Hung
58f31096ab
Zero out ports
2019-09-26 13:40:38 -07:00
Eddie Hung
af59856ba1
xilinx_dsp_cascade to also cascade AREG and BREG
2019-09-26 13:29:18 -07:00
Eddie Hung
832216dab0
Try recursive pmgen for P cascade
2019-09-26 12:09:57 -07:00
Eddie Hung
bd8661e024
CREG to check for \keep
2019-09-26 10:32:01 -07:00
Eddie Hung
c0bb1d22e8
Remove newline
2019-09-26 10:31:55 -07:00
Eddie Hung
f1de93edf5
Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)
2019-09-25 22:58:03 -07:00
Eddie Hung
cd8a640989
Reject if (* init *) present
2019-09-25 18:21:08 -07:00
Eddie Hung
aeb1539818
Rework xilinx_dsp postAdd for new wreduce call
2019-09-25 17:22:30 -07:00
Eddie Hung
5f8917c984
Fix memory issue since SigSpec& could be invalidated
2019-09-25 16:45:51 -07:00
Eddie Hung
486dd7c483
unextend only used in init
2019-09-25 14:05:59 -07:00
Eddie Hung
53ea5daa42
Call 'wreduce' after mul2dsp to avoid unextend()
2019-09-25 14:04:36 -07:00
Clifford Wolf
b432c9b44b
Improve "portlist" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-25 09:20:38 +02:00
Clifford Wolf
6c427d36dd
Add "portlist" command
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-24 18:08:59 +02:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
e556d48d45
Set [AB]CASCREG to legal values
2019-09-23 16:00:11 -07:00
Eddie Hung
b824a56cde
Comment to explain separating CREG packing
2019-09-23 13:58:10 -07:00
Eddie Hung
15dfbc8125
Separate out CREG packing into new pattern, to avoid conflict with PREG
2019-09-23 13:27:10 -07:00
Eddie Hung
26a6c55665
Move log_debug("\n") later
2019-09-23 13:27:00 -07:00
Eddie Hung
d0dbbc2605
Move unextend initialisation later
2019-09-23 13:26:34 -07:00
Eddie Hung
a67af3d5e5
Use new port() overload once more
2019-09-23 13:00:44 -07:00
Eddie Hung
bcee87a457
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-23 10:58:28 -07:00
N. Engelhardt
3bed4cb18a
fix show command for macos
2019-09-23 17:47:05 +02:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Eddie Hung
53817b8575
Use new port/param overload in pmg
2019-09-20 14:21:22 -07:00
Eddie Hung
d122083a11
Output pattern matcher items as log_debug()
2019-09-20 12:42:28 -07:00
Eddie Hung
95644b00cb
OPMODE is port not param
2019-09-20 12:37:29 -07:00
Eddie Hung
3fb839e255
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-20 12:21:36 -07:00
Eddie Hung
eb597431f0
Do not run xilinx_dsp_cascadeAB for now
2019-09-20 12:18:37 -07:00
Eddie Hung
0bca366bcd
WIP for xiinx_dsp_cascadeAB
2019-09-20 12:07:14 -07:00
Eddie Hung
b0ad2592be
Run until convergence
2019-09-20 12:04:16 -07:00
Eddie Hung
1b892ca1be
Cleanup ice40_dsp.pmg
2019-09-20 12:03:45 -07:00
Eddie Hung
d88903e610
Cleanup xilinx_dsp
2019-09-20 12:03:25 -07:00
Eddie Hung
1809f463fb
More exceptions
2019-09-20 12:03:10 -07:00
Eddie Hung
70c5444b25
Update doc
2019-09-20 10:07:54 -07:00
Eddie Hung
ed187ef1cf
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
2019-09-20 10:00:09 -07:00
Eddie Hung
1844498c5f
Add an overload for port/param with default value
2019-09-20 09:59:42 -07:00
Eddie Hung
a0d3ecf8c6
Small cleanup
2019-09-20 08:41:28 -07:00
Clifford Wolf
1f64b34c64
Add "add -mod"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-20 10:27:17 +02:00
Eddie Hung
8cfcaf108e
Disable support for SB_MAC16 reset since it is async
2019-09-19 22:48:57 -07:00
Eddie Hung
a59f80834f
SB_MAC16 ffCD to not pack same as ffO
2019-09-19 22:39:47 -07:00
Eddie Hung
1b88211ec6
Clarify
2019-09-19 21:58:34 -07:00
Eddie Hung
34f9a8ceb2
Update doc for ice40_dsp
2019-09-19 21:57:11 -07:00
Eddie Hung
8a94ce7aa5
Add an index
2019-09-19 20:04:44 -07:00
Eddie Hung
c83a667555
Fix width of D
2019-09-19 18:08:46 -07:00
Eddie Hung
a8bc460805
Use ID() macro
2019-09-19 16:13:22 -07:00
Eddie Hung
b88f0f6450
Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp
2019-09-19 15:47:41 -07:00
Eddie Hung
37b0fc17e3
Re-enable sign extension for C input
2019-09-19 15:40:17 -07:00
Eddie Hung
64a72ed51e
Do not perform width-checks for DSP48E1 which is much more complicated
2019-09-19 14:50:11 -07:00
Eddie Hung
517ca49963
Remove TODO as check should not be necessary
2019-09-19 14:49:47 -07:00
Eddie Hung
307b2dc8e5
Revert index to select
2019-09-19 14:46:53 -07:00
Eddie Hung
ea5e5a212e
Cleanup xilinx_dsp too
2019-09-19 14:34:06 -07:00
Eddie Hung
1a0f7ed09c
Refactor ce{mux,pol} -> hold{mux,pol}
2019-09-19 14:27:25 -07:00
Eddie Hung
429c9852ce
Add HOLD/RST support for SB_MAC16
2019-09-19 14:02:55 -07:00
Eddie Hung
2766465a2b
Add support for SB_MAC16 CD and H registers
2019-09-19 12:14:33 -07:00
Eddie Hung
c8310a6e76
Refactor ice40_dsp.pmg
2019-09-19 12:00:48 -07:00
Clifford Wolf
b76fac3ac3
Add techmap_autopurge attribute, fixes #1381
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-19 20:00:52 +02:00
Eddie Hung
29d446d758
Cleanup
2019-09-19 10:39:00 -07:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
70c607d7dd
Document (* gentb_skip *) attr for test_autotb
2019-09-18 12:41:35 -07:00
Eddie Hung
f7dbfef792
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:40:21 -07:00
Eddie Hung
b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
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peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
2019-09-18 12:40:08 -07:00
Eddie Hung
44bf4ac35c
Add doc on pattern detector for overflow
2019-09-18 12:35:24 -07:00
Eddie Hung
fd3b033903
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-18 12:23:22 -07:00
Eddie Hung
347cbf59bd
Check overflow condition is power of 2 without using int32
2019-09-18 12:16:03 -07:00
Eddie Hung
1f18736d20
Add support for overflow using pattern detector
2019-09-18 09:39:59 -07:00
Eddie Hung
0932e23dff
Separate dffrstmux from dffcemux, fix typos
2019-09-18 09:34:42 -07:00
Eddie Hung
2b93b8fc74
Merge pull request #1374 from YosysHQ/eddie/fix1371
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Fix two non-deterministic behaviours that cause divergence between compilers
2019-09-15 13:56:07 -07:00
Eddie Hung
14d72c39c3
Revert "Make one check $shift(x)? only; change testcase to be 8b"
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This reverts commit e2c2d784c8
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2019-09-13 16:33:18 -07:00
Eddie Hung
9a73adde50
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
Eddie Hung
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
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2019-09-13 09:49:15 -07:00
Clifford Wolf
a67d63714b
Fix handling of z_digit "?" and fix optimization of cmp with "z"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-13 13:39:39 +02:00