930d98f2af
[test] deploy new tests
2023-07-08 21:52:16 -07:00
51e1547634
[test] hotfix
2023-06-26 15:32:16 -07:00
270d6f933b
[test] add a new testcase to validate mock wrapper
2023-06-26 15:26:50 -07:00
919d6d8608
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
2023-06-25 22:49:51 -07:00
523e338d53
[test] debugging
2023-06-23 14:49:52 -07:00
962ba67e36
[test] adding new tests to validate fpga core wrapper naming rules
2023-06-23 14:47:21 -07:00
97b089ae3c
[test] added new testcases to validate fpga core wrapper
2023-06-18 21:01:37 -07:00
1ef8eed589
[test] update no time stamp golden outputs
2023-06-08 15:38:15 -07:00
31b16ba9d7
[test] fixed a few bugs
2023-05-27 12:47:57 -07:00
27b8007d1b
[test] rework pcf support testcase for mock wrapper
2023-05-27 12:45:29 -07:00
b3471f2703
[test] swap test name
2023-05-27 12:34:10 -07:00
89f184e779
[test] fixed a few bugs
2023-05-27 12:19:28 -07:00
e1feebc96d
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
2023-05-26 21:54:08 -07:00
205e9aa67b
[test] add a new test case
2023-05-26 20:55:52 -07:00
7fbe567d4c
[test] add more testcases
2023-05-25 20:24:02 -07:00
812553e13d
[test] adding more test cases
2023-05-25 20:17:23 -07:00
11832ad22c
[test] add a new testcase to validate mock wrapper
2023-05-25 20:02:10 -07:00
8d02a6e600
[test] now testcases are using proper arch
2023-05-03 21:47:21 +08:00
df771cb33a
[test] add a new testcase for subtile and deploy it to basic regression test
2023-05-03 15:41:29 +08:00
f06248a1b0
[test] add a new testcase to validate the ccff v2
2023-04-24 14:55:22 +08:00
02e964b16f
[test] add a new test case for ccffv2
2023-04-22 15:41:19 +08:00
fba0a83679
[test] debugging 2-clock network
2023-04-20 14:44:01 +08:00
02b02d18a5
[test] fixed a bug in clock arch
2023-04-20 11:35:36 +08:00
b242fd97d6
[test] adding new arch and testcase for 2-clock network
2023-04-20 11:31:49 +08:00
03cb664049
[test] now clock network example script supports multiple clocks
2023-04-20 10:56:36 +08:00
7d333b3669
[test] add a new test for clock network: validate full testbench is working
2023-04-20 10:36:08 +08:00
1f9c1fe7e1
[test] clean up clock network task config
2023-04-20 10:31:22 +08:00
fd1c4039d3
[test] typo
2023-03-02 21:37:24 -08:00
02b50e3464
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
2023-03-02 21:33:32 -08:00
b9f7c72a96
[test] fixed some bugs in arch
2023-03-02 18:16:59 -08:00
780dec6b1b
[test] add a new test to validate the programmable clock arch
2023-02-28 21:46:57 -08:00
f586229b97
[test] enable rst_on_lut benchmark
2023-01-18 19:45:41 -08:00
b7a66705e0
[test] now use yosys_vpr flow; add rst_on_lut benchmark
2023-01-18 19:42:50 -08:00
e974e5ddf7
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
2023-01-18 18:31:36 -08:00
03273371c0
[test] add a new test to validate local reset
2023-01-18 18:17:14 -08:00
2c9593c1d4
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
2023-01-15 13:09:40 -08:00
13aed6fff5
[test] still commment verification out
2023-01-15 12:17:59 -08:00
758cc7a089
[test] debugging
2023-01-15 11:44:48 -08:00
14bb76ec87
[test] remove verification steps for new test but leave a todo
2023-01-14 23:06:54 -08:00
9222d085cd
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
2023-01-13 22:04:56 -08:00
26f71656de
[test] update pin constraints
2023-01-13 21:12:18 -08:00
93107c752a
[test] updating test case
2023-01-13 19:53:15 -08:00
1353577351
[test] added a new test to validate locally generated clocks
2023-01-13 16:45:30 -08:00
c7dc3ce7dc
[test] pass
2023-01-11 17:10:29 -08:00
f6f153ace4
[test] debugging
2023-01-11 17:06:31 -08:00
d5ebbeea9a
[test] adding a new test to show how to automate generation of bus group files
2023-01-11 16:59:54 -08:00
83d7ff56e1
[script] add dedicated testcase for source commands
2023-01-01 17:04:24 -08:00
d7a95a8ec2
[script] fixed some bugs
2022-12-30 18:30:52 -08:00
56a3e6e463
[test] reduce test size
2022-12-30 18:28:17 -08:00
ae11a4fbf2
[test] add a new test case
2022-12-30 18:25:15 -08:00
513f7800aa
[test] update golden outputs for no_cout_in_gsb testcase
2022-11-03 17:51:51 -07:00
a88bc2d4de
[test] update golden outputs for device4x4
2022-11-03 17:51:08 -07:00
5f74367c2e
[test] update golden for device1x1 no time stamp netlists
2022-11-03 17:48:40 -07:00
00a485cbeb
[test] add missing file
2022-10-17 19:44:25 -07:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
8b00bfdff9
[test] replace hardcoded paths in task config files with relative paths
2022-10-17 11:55:57 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
b0be27b384
[test] add repack design constraints files
2022-10-13 11:22:48 -07:00
7f67794787
[arch]add new arch to test
2022-10-13 10:54:40 -07:00
4eaecde0b9
[test] add golden netlists to ensure no cout in gsb
2022-10-01 11:03:13 -07:00
78f30cf072
[test] add a new test to track the golden netlists where cout is not in GSB
2022-09-30 15:38:27 -07:00
3f8e2ade2e
[script] update missing scripts required by pb_pin_fixup test cases
2022-09-29 13:39:46 -07:00
49fa783914
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00
b532bca9d2
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
2022-09-21 10:54:16 -07:00
36603f9772
Merge branch 'master' into vtr_upgrade
2022-09-20 21:08:06 -07:00
b8f1520367
[test] fixed a bug
2022-09-20 18:12:23 -07:00
4e254a304d
[test] now golden netlists have no relationship with OPENFPGA_PATH
2022-09-20 18:10:52 -07:00
5e23be19a5
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
2022-09-20 18:07:31 -07:00
1b0b50b928
[test] update golden netlist
2022-09-20 16:04:05 -07:00
846ca26311
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
2022-09-20 12:08:24 -07:00
10e86d334a
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
2022-09-16 10:29:19 -07:00
330785635d
[test] now use a bigger fabric for the test case on custom I/O location
2022-09-13 17:53:33 -07:00
0d6e4e3979
[test] add a new example for the repack options
2022-09-12 16:21:49 -07:00
1ab7590603
[test] added a new test case to
2022-09-09 16:59:06 -07:00
d4523e819c
[test] fixed a bug
2022-09-08 16:55:50 -07:00
d76f3e3b6c
[test] fixed the bug
2022-09-08 16:34:23 -07:00
218e6d0a47
[arch] fixed syntax errors
2022-09-08 16:31:52 -07:00
a840aeea7a
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
2022-09-08 16:27:11 -07:00
477e2119d7
[test] remove abs paths in golden outputs without time stamps
2022-09-06 15:24:43 -07:00
93ab992187
[test] update golden outputs without time stamps
2022-09-06 14:59:00 -07:00
561d0a6545
[test] add more test case to track golden outputs for representative fpga sizes
2022-09-06 14:04:23 -07:00
51dc082bd4
[test] force a fixed routing chan W for no time stamp test case
2022-09-01 15:02:40 -07:00
d86eb04c5d
[test] now no timestamp test case covers gsb files
2022-09-01 14:03:51 -07:00
069e2b00b1
[test] add more test cases to validate gsb options
2022-08-29 22:03:06 -07:00
8b17bf1b1c
[test] add a new test case to validate that .act file is not required when power analysis flow is off
2022-08-01 18:44:47 -07:00
35fe858035
[test] fixed a few bugs
2022-07-28 12:06:16 -07:00
ca9122ddb9
[test] fixed a bug
2022-07-28 11:57:47 -07:00
ec31e124b7
[test] reworked test case on pcf2place
2022-07-28 11:51:56 -07:00
cfc0d08060
Add constrain_pin_location command in openfpga; add full flow test.
2022-07-20 11:51:00 -07:00
6719a9aa26
[test] update golden netlists/testbenches etc.
2022-05-22 13:03:01 +08:00
22c4d72358
[test] add a test case to validate negative edge-triggered ff
2022-05-09 16:57:42 +08:00
efc25aa66e
[Script] Fixed a bug in wrong paths
2022-04-13 16:04:33 +08:00
5beefda3bd
[Test] Add a new test case to validate the fix_pins option
2022-04-13 15:55:21 +08:00
f8845f7d3a
[Test] Add a test case to validate separated clock pins in global port
2022-03-20 11:02:07 +08:00
fdaf97e60d
[Test] Update test case by using GPIO with config_done signals
2022-02-24 09:49:34 -08:00
a615c9d4e3
[Test] Rename test cases
2022-02-24 09:43:41 -08:00
b27a04eb24
[Test] Now test case has a config done CCFF
2022-02-23 22:07:11 -08:00
245c7b1e45
[Test] Add a new test case to validate config enable signal in preconfigured testbenches
2022-02-23 16:02:00 -08:00
e33ba667e4
[Test] Add missing file
2022-02-20 10:59:44 -08:00
f30de1085c
[Test] Cover all the related testcase about bus group
2022-02-19 23:33:16 -08:00
b4202f52b4
[Test] debugging
2022-02-19 23:26:29 -08:00
785bb1633d
[Test] trying to see if we support busgroup per benchmark in task configuration file
2022-02-19 23:23:36 -08:00
7645d5332d
[Test] Update bug group examples on the big endian support
2022-02-18 23:09:03 -08:00
f0ce1e79a3
[Test] Added a new test to validate bus group in full testbench
2022-02-18 15:43:21 -08:00
223575cf3e
[Test] Added a new test for bus group on full testbenches
2022-02-18 15:33:29 -08:00
5ab84e1861
[Test] Add a new test for bus group
2022-02-18 15:29:33 -08:00
b4d59fdd1e
[Test] Update bus group file due to little and big endian conversion during yosys/vpr
2022-02-18 15:02:08 -08:00
36543f7f2f
[Script] Support simplified rewriting for Yosys on output verilog
2022-02-18 14:54:39 -08:00
8ba3d06392
[Test] Fixed bugs in simulation settings
2022-02-18 12:36:22 -08:00
a4d5172b7c
[Test] Fixed bugs that causes VPR failed
2022-02-18 12:31:29 -08:00
7176037bc4
[Test] Added a new test about bus group
2022-02-18 12:26:00 -08:00
f002c79a61
[Test] Adapt pin constraints due to changes in pin names
2022-02-15 16:06:46 -08:00
b533fd17d5
[Test] Rework pin constraints that cause problems
2022-02-15 15:41:16 -08:00
9ef7ad64d8
[Test] Simplify paths
2022-02-15 15:35:21 -08:00
f8ef3df560
[Test] Now use 4x4 fabric in testing write_rr_gsb commands
2022-01-26 11:41:48 -08:00
3b7588cd48
[Test] Rename test case to be consistent with the name of options
2022-01-26 11:25:54 -08:00
6b26ed0819
[Test] Add test cases on writing gsb files
2022-01-26 11:22:39 -08:00
23795d6474
[Test] Update golden netlists
2022-01-25 20:37:08 -08:00
a9e6b7c12e
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
2022-01-25 20:33:49 -08:00
fedb1bd2e3
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
2022-01-25 16:41:36 -08:00
6e778a74ee
[Test] Add golden reference for files outputted without time stamp
2022-01-25 16:24:25 -08:00
2bee59c6ca
[Test] Add the testcase to validate ``--no_time_stamp``
2022-01-25 16:21:15 -08:00
758453f725
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
2022-01-21 02:21:00 +05:00
397f2e71f1
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
2022-01-19 20:43:26 +05:00
588ee14920
Merge branch 'master' into issue-483
2022-01-18 13:38:12 +05:00
6a4cc340a3
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
2022-01-17 13:21:29 +05:00
598c5e6b75
Test case for yosys-only flow added
2022-01-14 15:37:47 +05:00
1ea56b2d18
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-11-18 00:00:55 +05:00
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
b2c4e3314e
[Test] Bug fix in test cases
2021-10-11 10:28:09 -07:00
8566e2a0cd
[Test] Renaming test case to follow naming convention as other fabric key test cases
2021-10-11 09:56:23 -07:00
b8b02d37d5
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
2021-10-11 09:53:23 -07:00
6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
b0aaab9c03
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
2021-09-22 11:32:13 -07:00
abfa380333
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
2021-09-22 11:27:09 -07:00
51fc222d61
[Test] Added a new test case for multi-region QL memory bank
2021-09-22 10:01:33 -07:00
1412121541
[Test] Added a new test to validate the fabric key parser for QL memory bank
2021-09-21 16:20:24 -07:00
dc2d1d1c3c
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
2021-09-21 15:42:20 -07:00
60fc3ab36c
[Test] Added a new test case for the WLR memory bank
2021-09-20 11:20:36 -07:00
b82cfdf555
[Test] Add the QL memory bank test to regression test cases
2021-09-09 09:29:21 -07:00
64dcdaec61
[Test] Update all the tasks that use counter benchmark
2021-07-02 17:29:13 -06:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
3aacce2a96
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 14:04:42 -06:00
edd5be2cae
[CI] Added testcase for benchmark variable
2021-07-02 12:51:34 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
9eeec05a1f
[Test] Bug fix
2021-06-29 19:55:07 -06:00
f32ffb6d61
[Test] Bug fix
2021-06-29 18:51:28 -06:00
c6089385b0
[Misc] Bug fix
2021-06-29 18:34:41 -06:00
5f5a03f17f
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
2021-06-29 18:28:38 -06:00
2c1692e6dc
[Test] Bug fix
2021-06-29 17:54:25 -06:00
30c2f597f2
[Test] Added two cases to validate testbench generation without self checking
2021-06-29 16:06:15 -06:00
c62666e7c3
[Test] Use proper template for some failing tests
2021-06-09 14:24:34 -06:00
462326aaa5
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
2021-06-07 21:50:00 -06:00
5ecd975ec7
[Test] Bug fix
2021-06-07 19:20:10 -06:00
9556f994b4
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
2021-06-07 17:49:40 -06:00
a67196178e
[Test] Now use 'write_full_testbench' in configuration frame test cases
2021-06-07 13:58:15 -06:00
27fa15603a
[Tool] Patch test case due to changes in the template script
2021-06-04 18:17:47 -06:00
5f96d440ec
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
2021-06-04 11:48:05 -06:00
ec203d3a5c
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
2021-06-04 11:35:23 -06:00
2068291de0
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
2021-06-04 11:32:49 -06:00
aa4e1f5f9a
[Test] Update test case which uses write_full_testbench openfpga shell script
2021-06-04 11:29:43 -06:00
ebe30fc070
[Test] Deploy write full testbench to multi-head configuration chain test case
2021-06-03 17:08:33 -06:00
1e9f6eb439
[Test] update configuration chain test to use new testbench
2021-06-03 15:53:27 -06:00
f1658cb735
[Test] Deploy blinking to test cases
2021-05-06 15:17:45 -06:00
8046b16c15
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
2021-04-21 14:04:34 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
a4893e27cf
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
2021-04-11 17:26:27 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
91f12071d5
[Test] Use counter4bit in the multi-clock test
2021-01-13 13:34:59 -07:00
250adb01cf
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
2021-01-13 13:18:31 -07:00
99e2a068fb
[Test] Add a test case for multi-clock
2021-01-12 18:06:25 -07:00
43418cd76b
[Test] Deploy pipeplined and2 to test cases
2021-01-10 10:28:22 -07:00
06af30ef10
[Test] Add test case for the SCFF usage in configuration chain
2021-01-04 17:30:19 -07:00
6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev
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Support Delay Customization in OpenFPGA Task Configuration File
2020-12-08 15:32:48 -07:00
tangxifan
taoli4rs
Aram Kostanyan
Awais Abbas
nadeemyaseen-rs
Ganesh Gore
AurelienAlacchi