tangxifan
|
d264b39dab
|
[test] update golden
|
2024-11-13 20:13:02 -08:00 |
|
tangxifan
|
e863333f22
|
[test] relax route W to bypass VPR bugs
|
2024-11-13 19:01:55 -08:00 |
Lin
|
3c219967df
|
add testcase
|
2024-11-01 12:15:08 +08:00 |
|
tangxifan
|
c41c142331
|
[test] update golden
|
2024-10-17 17:01:05 -07:00 |
|
tangxifan
|
b6b75fd19c
|
[test] bypass vtr bugs
|
2024-10-17 14:58:56 -07:00 |
|
Lin
|
fc5c0f6965
|
modified testcases
|
2024-10-09 17:41:01 +08:00 |
|
Lin
|
88e12a0afa
|
modified test cases & xsd file
|
2024-10-09 17:21:49 +08:00 |
Jingrong Lin
|
be3546f7e3
|
Merge branch 'master' into bin_format
|
2024-10-08 13:28:53 +08:00 |
|
tangxifan
|
aa86381d65
|
[test] adjust route chan width to avoid vpr bug on min route chan width (some case failed)
|
2024-10-07 17:17:36 -07:00 |
|
Lin
|
20238c1a2d
|
modified testcase
|
2024-09-29 12:30:39 +08:00 |
|
Lin
|
6864159f31
|
modified testcases
|
2024-09-29 11:20:46 +08:00 |
|
Lin
|
87ca9f3006
|
add three testcases to test bin read and write
|
2024-09-29 11:09:01 +08:00 |
|
tangxifan
|
33a253da3d
|
[core] fixed the bug
|
2024-09-20 22:20:41 -07:00 |
|
tangxifan
|
6551ca81e5
|
[core] debugging
|
2024-09-20 19:48:02 -07:00 |
|
tangxifan
|
6d3d36626e
|
[test] typo
|
2024-09-20 19:29:47 -07:00 |
|
tangxifan
|
ed33b62a60
|
[test] add new tests to validate intermediate drivers in clock
|
2024-09-20 19:27:40 -07:00 |
|
Jingrong Lin
|
77b188060b
|
Merge branch 'master' into preloading_clean
|
2024-09-11 11:08:49 +08:00 |
victorzh001
|
04a60ca4b5
|
Merge branch 'master' into victor_OpenFPGA_dbg
|
2024-09-10 11:01:47 +08:00 |
|
tangxifan
|
f912af513b
|
[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
|
2024-09-09 13:54:20 -07:00 |
Victor
|
8d97ebd980
|
Add more test cases and update documentation about the YAML file format of this command
|
2024-09-09 17:49:10 +08:00 |
|
Lin
|
d15025d9d2
|
add a task case to ease the use of compress_routing option
|
2024-09-09 14:18:47 +08:00 |
|
Victor
|
7bacc781d0
|
update code according to code review comments
|
2024-09-06 15:39:08 +08:00 |
|
Lin
|
1d35a17a8b
|
delete redundant file
|
2024-08-30 14:18:59 +08:00 |
|
Lin
|
acce64058c
|
add test case
|
2024-08-30 14:17:42 +08:00 |
|
Lin
|
701a7a5c52
|
add test case
|
2024-08-26 02:45:57 -07:00 |
|
Lin
|
88fa9f8d39
|
add test case
|
2024-08-25 23:41:19 -07:00 |
|
tangxifan
|
2c35840457
|
[test] add a new test to validate CHANY clock spin in DEC
|
2024-08-15 14:24:31 -07:00 |
|
tangxifan
|
586dd1a510
|
[test] add a new and strong test to validate the disable unused clock spines
|
2024-08-15 10:24:58 -07:00 |
|
tangxifan
|
84cc7090ce
|
[test] add a new test to validate that pb pin fixup impacts global net now
|
2024-08-14 10:37:46 -07:00 |
|
tangxifan
|
c6246ae905
|
[test] typo
|
2024-08-09 17:10:51 -07:00 |
|
tangxifan
|
38f1bdba4e
|
[test] add a new test case
|
2024-08-09 17:04:10 -07:00 |
|
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
|
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |
|
tangxifan
|
84c2b27c7b
|
[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
|
2024-08-02 17:24:44 -07:00 |
|
tangxifan
|
3181f2d5a3
|
[test] add a new test to validate multiple entry points for a clock network
|
2024-07-30 14:17:14 -07:00 |
|
tangxifan
|
687f03fd77
|
[test] add a new test to validate clock network on module named by index
|
2024-07-30 14:06:53 -07:00 |
|
tangxifan
|
f9f9aab7d9
|
[test] typo
|
2024-07-30 12:50:14 -07:00 |
|
tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
|
2024-07-30 12:48:35 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
dbe8e63f53
|
[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |
|
tangxifan
|
77304164f4
|
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
|
2024-07-10 10:13:41 -07:00 |
|
tangxifan
|
191a3d1c5e
|
[test] update W
|
2024-07-10 10:01:31 -07:00 |
|
tangxifan
|
81fe722d98
|
[test] adjust W
|
2024-07-09 23:49:01 -07:00 |
|
tangxifan
|
43dbeafd44
|
[test] typo
|
2024-07-09 20:27:28 -07:00 |
|
tangxifan
|
9ce4b57363
|
[test] typo
|
2024-07-09 20:25:39 -07:00 |
|
tangxifan
|
e5d146a67a
|
[test] add new tests to validate rst on lut and clk on lut features
|
2024-07-09 20:24:23 -07:00 |
|
tangxifan
|
5efc9d0e00
|
[test] update golden outputs
|
2024-07-08 23:24:16 -07:00 |