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[test] bypass vtr bugs

This commit is contained in:
tangxifan 2024-10-17 14:58:56 -07:00
parent 529a93bee9
commit b6b75fd19c
1 changed files with 2 additions and 0 deletions
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2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
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@ -48,6 +48,8 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_r
bench1_top = clk_on_lut
bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml
# Triggered a bug in VPR, when route_chan_width=40, it failed
bench1_openfpga_vpr_route_chan_width=44
bench2_top = rst_and_clk_on_lut
bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml