diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
index 292458942..64ee22a50 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf
@@ -48,6 +48,8 @@ bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_r
 
 bench1_top = clk_on_lut
 bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk.xml
+# Triggered a bug in VPR, when route_chan_width=40, it failed
+bench1_openfpga_vpr_route_chan_width=44
 
 bench2_top = rst_and_clk_on_lut
 bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml