Add more test cases and update documentation about the YAML file format of this command

docs/source/manual/file_formats/reference_file.rst

@@ -0,0 +1,80 @@
+.. _file_format_reference_file:
+
+Reference File (.yaml)
+----------------------------------------
+
+This file is generated by command :ref:`openfpga_setup_commands_report_reference`
+
+
+The reference file aims to the show reference number of each child module of given parent module
+
+By using the options of the command :ref:`openfpga_setup_commands_report_reference`, user can selectively output the reference info under the given parent module on their needs.
+
+An example of the file is shown as follows.
+
+.. code-block:: yaml
+
+Date: Mon Sep  9 16:41:53 2024
+
+#the instance names are given during netlist generation
+references:
+- module: grid_io_top
+  count: 1
+  instances:
+    - grid_io_top_1__2_
+- module: grid_io_right
+  count: 1
+  instances:
+    - grid_io_right_2__1_
+- module: grid_io_bottom
+  count: 1
+  instances:
+    - grid_io_bottom_1__0_
+- module: grid_io_left
+  count: 1
+  instances:
+    - grid_io_left_0__1_
+- module: grid_clb
+  count: 1
+  instances:
+    - grid_clb_1__1_
+- module: sb_0__0_
+  count: 1
+  instances:
+    - sb_0__0_
+- module: sb_0__1_
+  count: 1
+  instances:
+    - sb_0__1_
+- module: sb_1__0_
+  count: 1
+  instances:
+    - sb_1__0_
+- module: sb_1__1_
+  count: 1
+  instances:
+    - sb_1__1_
+- module: cbx_1__0_
+  count: 1
+  instances:
+    - cbx_1__0_
+- module: cbx_1__1_
+  count: 1
+  instances:
+    - cbx_1__1_
+- module: cby_0__1_
+  count: 1
+  instances:
+    - cby_0__1_
+- module: cby_1__1_
+  count: 1
+  instances:
+    - cby_1__1_
+          direct_interc
+
+In this example, the parent module is ``fpga_top``.
+The child modules under ``fpga_top`` are ``grid_io_top``, ``grid_io_right``, and etc.
+
+The instance of the child module ``grid_io_top`` is shown as a list as below:
+    - grid_io_top_1__2_
+

openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga

@@ -26,7 +26,9 @@ lut_truth_table_fixup
 build_fabric --compress_routing --frame_view #--verbose
 
 # Report reference to a file
-report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS}
+report_reference ${OPENFPGA_REPORT_REFERENCE_MODULE_OPTIONS}
+report_reference ${OPENFPGA_REPORT_REFERENCE_VERBOSE_OPTIONS}
+report_reference ${OPENFPGA_REPORT_REFERENCE_NO_TIME_STAMP_OPTIONS}
 
 # Finish and exit OpenFPGA
 exit

openfpga_flow/tasks/basic_tests/report_reference/config/task.conf

@@ -19,7 +19,9 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-openfpga_report_reference_options=--file reference_info.yaml --module grid_io_right
+openfpga_report_reference_module_options=--file reference_module.yaml --module fpga_top
+openfpga_report_reference_verbose_options=--file reference_verbose.yaml --module fpga_top --verbose
+openfpga_report_reference_no_time_stamp_options=--file reference_no_time_stamp.yaml --module grid_io_right --no_time_stamp
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml