add test case
This commit is contained in:
Lin
parent
adeb9ba7ea
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Optionally pb pin fixup
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${OPENFPGA_PB_PIN_FIXUP_COMMAND}
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# preload unique blocks from the provided xml file
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read_unique_blocks --file ${READ_UNIQUE_BLOCKS_XML} --verbose --type xml
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
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write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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# FIXME: Not supported yet.
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#write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -0,0 +1,80 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling ideal ${OPENFPGA_VPR_EXTRA_OPTIONS}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Optionally pb pin fixup
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${OPENFPGA_PB_PIN_FIXUP_COMMAND}
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --group_tile ${OPENFPGA_GROUP_TILE_CONFIG_FILE} #--verbose
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#write unique blocks xml file
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write_unique_blocks --file ./write_unique_block.xml --verbose --type xml
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
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write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} ${OPENFPGA_VERILOG_TESTBENCH_OPTIONS}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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# FIXME: Not supported yet.
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#write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -21,6 +21,9 @@ run-task basic_tests/preload_rr_graph/preload_rr_graph_bin $@
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echo -e "Testing preloading unique blocks"
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run-task basic_tests/preload_unique_blocks/write_unique_blocks $@
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run-task basic_tests/preload_unique_blocks/read_unique_blocks $@
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run-task basic_tests/preload_unique_blocks/write_unique_blocks_full_flow $@
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run-task basic_tests/preload_unique_blocks/read_unique_blocks_full_flow $@
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echo -e "Testing testbenches using fpga core wrapper"
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run-task basic_tests/full_testbench/fpga_core_wrapper $@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = false
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/read_unique_blocks_full_flow_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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read_unique_blocks_xml =${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/preload_unique_blocks/read_unique_blocks_full_flow/read_unique_block.xml
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openfpga_vpr_extra_options=
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openfpga_pb_pin_fixup_command=
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openfpga_vpr_device=4x4
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openfpga_vpr_route_chan_width=20
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openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
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openfpga_verilog_testbench_options=--explicit_port_mapping
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = or2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1 @@
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<tiles style="top_left"/>
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@ -0,0 +1,92 @@
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<unique_blocks>
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<block type="sb" x="0" y="0">
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</block>
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<block type="sb" x="0" y="1">
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<instance x="0" y="2"/>
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<instance x="0" y="3"/>
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</block>
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<block type="sb" x="0" y="4">
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</block>
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<block type="sb" x="1" y="0">
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<instance x="2" y="0"/>
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<instance x="3" y="0"/>
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</block>
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<block type="sb" x="1" y="1">
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<instance x="1" y="2"/>
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<instance x="1" y="3"/>
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<instance x="2" y="1"/>
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<instance x="2" y="2"/>
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<instance x="2" y="3"/>
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<instance x="3" y="1"/>
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<instance x="3" y="2"/>
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<instance x="3" y="3"/>
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</block>
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<block type="sb" x="1" y="4">
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<instance x="2" y="4"/>
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<instance x="3" y="4"/>
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</block>
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<block type="sb" x="4" y="0">
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</block>
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<block type="sb" x="4" y="1">
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<instance x="4" y="2"/>
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<instance x="4" y="3"/>
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</block>
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<block type="sb" x="4" y="4">
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</block>
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<block type="cbx" x="1" y="0">
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<instance x="0" y="0"/>
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<instance x="0" y="1"/>
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<instance x="0" y="2"/>
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<instance x="0" y="3"/>
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<instance x="0" y="4"/>
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<instance x="2" y="0"/>
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<instance x="3" y="0"/>
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<instance x="4" y="0"/>
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</block>
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<block type="cbx" x="1" y="1">
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<instance x="1" y="2"/>
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<instance x="1" y="3"/>
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<instance x="2" y="1"/>
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<instance x="2" y="2"/>
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<instance x="2" y="3"/>
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<instance x="3" y="1"/>
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<instance x="3" y="2"/>
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<instance x="3" y="3"/>
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<instance x="4" y="1"/>
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<instance x="4" y="2"/>
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<instance x="4" y="3"/>
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</block>
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<block type="cbx" x="1" y="4">
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<instance x="2" y="4"/>
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<instance x="3" y="4"/>
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<instance x="4" y="4"/>
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</block>
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<block type="cby" x="0" y="1">
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<instance x="0" y="0"/>
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<instance x="0" y="2"/>
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<instance x="0" y="3"/>
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<instance x="0" y="4"/>
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<instance x="1" y="0"/>
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<instance x="2" y="0"/>
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<instance x="3" y="0"/>
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<instance x="4" y="0"/>
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</block>
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<block type="cby" x="1" y="1">
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<instance x="1" y="2"/>
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<instance x="1" y="3"/>
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<instance x="1" y="4"/>
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<instance x="2" y="1"/>
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<instance x="2" y="2"/>
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<instance x="2" y="3"/>
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<instance x="2" y="4"/>
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<instance x="3" y="1"/>
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<instance x="3" y="2"/>
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<instance x="3" y="3"/>
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<instance x="3" y="4"/>
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</block>
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<block type="cby" x="4" y="1">
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<instance x="4" y="2"/>
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<instance x="4" y="3"/>
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<instance x="4" y="4"/>
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</block>
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</unique_blocks>
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@ -0,0 +1,41 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = false
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_unique_blocks_full_flow_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_vpr_extra_options=
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openfpga_pb_pin_fixup_command=
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openfpga_vpr_device=4x4
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openfpga_vpr_route_chan_width=20
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openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
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openfpga_verilog_testbench_options=--explicit_port_mapping
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = or2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1 @@
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<tiles style="top_left"/>
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