[test] typo
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@ -3,6 +3,6 @@
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="rst"/>
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<set_io pin="op_clk[0]" net="OPEN"/>
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<set_io pin="op_clk[0]" net="clk"/>
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</pin_constraints>
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