diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml
index 28ab471d5..15df5148e 100644
--- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml
+++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut/config/pin_constraints_rst.xml
@@ -3,6 +3,6 @@
        - the reset signal to the op_reset[0] port of the FPGA fabric
     -->
   <set_io pin="op_reset[0]" net="rst"/>
-  <set_io pin="op_clk[0]" net="OPEN"/>
+  <set_io pin="op_clk[0]" net="clk"/>
 </pin_constraints>