[test] add new tests to validate intermediate drivers in clock
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tangxifan
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2bb87ea278
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ed33b62a60
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@ -262,6 +262,7 @@ run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup
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run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@
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run-task basic_tests/clock_network/homo_1clock_1reset_2layer_disable_unused_spines $@
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run-task basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver $@
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run-task basic_tests/clock_network/homo_1clock_1reset_2layer_intermediate_driver $@
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echo -e "Testing configuration chain of a K4N4 FPGA using .blif generated by yosys+verific";
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run-task basic_tests/verific_test $@
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@ -0,0 +1,37 @@
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" global_port="op_clk[0:1]">
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<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<intermediate_driver x="1" y="1">
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<tap from_pin="clb.O[0:7]" to_pin="op_clk[1:1]"/>
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</intermediate_driver>
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<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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<all from_pin="op_clk[0:0]" to_pin="clb[0:0].I[0:11]"/>
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<all from_pin="op_clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
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</taps>
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</clock_network>
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<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
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<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
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</taps>
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</clock_network>
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</clock_networks>
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@ -0,0 +1,35 @@
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]">
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<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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</taps>
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</clock_network>
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<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
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<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<intermediate_driver x="1" y="1">
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<internal_driver from_pin="clb.O[0:7]" to_pin="op_reset[0:0]"/>
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</intermediate_driver>
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<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1">
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<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1">
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<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
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</taps>
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</clock_network>
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</clock_networks>
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@ -0,0 +1,9 @@
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<pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="OPEN"/>
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<set_io pin="op_clk[0]" net="clk_i"/>
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<set_io pin="op_clk[1]" net="int_clk"/>
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</pin_constraints>
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@ -0,0 +1,8 @@
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<pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="int_rst"/>
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<set_io pin="op_clk[0]" net="clk_i"/>
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</pin_constraints>
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@ -0,0 +1,4 @@
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<repack_design_constraints>
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<!-- Intended to be dummy -->
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</repack_design_constraints>
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@ -0,0 +1,57 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = false
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spice_output=false
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verilog_output=true
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timeout_each_job = 3*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_int_driver_no_ace_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
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openfpga_vpr_device_layout=2x2
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openfpga_vpr_route_chan_width=32
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openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver.xml
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openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
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openfpga_route_clock_options=
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openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
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[SYNTHESIS_PARAM]
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# Yosys script parameters
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bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
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bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
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bench_read_verilog_options_common = -nolatches
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bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
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bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
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bench0_top = clk_cond
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bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml
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bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
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bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml
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bench1_top = rst_cond
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bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml
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bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml
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bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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vpr_fpga_verilog_formal_verification_top_netlist=
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@ -0,0 +1,12 @@
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<vpr_constraints tool_name="vpr">
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<partition_list>
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<partition name="q_o_part">
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<add_atom name_pattern="q_o"/>
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<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
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</partition>
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<partition name="int_clk_part">
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<add_atom name_pattern="int_clk*"/>
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<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
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</partition>
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</partition_list>
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</vpr_constraints>
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@ -0,0 +1,12 @@
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<vpr_constraints tool_name="vpr">
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<partition_list>
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<partition name="q_o_part">
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<add_atom name_pattern="q_o"/>
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<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
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</partition>
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<partition name="int_rst_part">
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<add_atom name_pattern="int_rst*"/>
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<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
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</partition>
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</partition_list>
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</vpr_constraints>
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