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[test] add a new testcase to validate 3-layer clock architecture

This commit is contained in:
tangxifan 2024-08-02 18:18:49 -07:00
parent eeaa3373c6
commit 91c4336a4a
6 changed files with 147 additions and 0 deletions
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1
openfpga_flow/regression_test_scripts/basic_reg_test.sh
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@ -243,6 +243,7 @@ run-task basic_tests/clock_network/homo_2clock_2layer $@
run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused $@
run-task basic_tests/clock_network/homo_2clock_2layer_disable_unused_tree $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer $@
run-task basic_tests/clock_network/homo_1clock_1reset_3layer_2entry $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_y_entry $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut $@
run-task basic_tests/clock_network/homo_1clock_1reset_2layer_syntax $@

72
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/clk_arch_1clk_1rst_3layer.xml Normal file
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@ -0,0 +1,72 @@
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]">
<spine name="clk_spine_lvl0_botm0" start_x="1" start_y="1" end_x="1" end_y="2">
<switch_point tap="clk_spine_lvl1_right" x="1" y="2"/>
</spine>
<spine name="clk_spine_lvl0_botm1" start_x="2" start_y="1" end_x="2" end_y="2">
<switch_point tap="clk_spine_lvl1_left" x="2" y="2"/>
</spine>
<spine name="clk_spine_lvl1_left" start_x="2" start_y="2" end_x="0" end_y="2">
<switch_point tap="clk_rib_lvl2_x0y2_upper" x="0" y="2"/>
<switch_point tap="clk_rib_lvl2_x0y2_lower" x="0" y="2"/>
<switch_point tap="clk_rib_lvl2_x1y2_upper" x="1" y="2"/>
<switch_point tap="clk_rib_lvl2_x1y2_lower" x="1" y="2"/>
</spine>
<spine name="clk_spine_lvl1_right" start_x="2" start_y="2" end_x="4" end_y="2">
<switch_point tap="clk_rib_lvl2_x2y2_upper" x="2" y="2"/>
<switch_point tap="clk_rib_lvl2_x2y2_lower" x="2" y="2"/>
<switch_point tap="clk_rib_lvl2_x3y2_upper" x="3" y="2"/>
<switch_point tap="clk_rib_lvl2_x3y2_lower" x="3" y="2"/>
<switch_point tap="clk_rib_lvl2_x4y2_upper" x="4" y="2"/>
<switch_point tap="clk_rib_lvl2_x4y2_lower" x="4" y="2"/>
</spine>
<spine name="clk_rib_lvl2_x0y2_upper" start_x="0" start_y="3" end_x="0" end_y="4"/>
<spine name="clk_rib_lvl2_x0y2_lower" start_x="0" start_y="2" end_x="0" end_y="0"/>
<spine name="clk_rib_lvl2_x1y2_upper" start_x="1" start_y="3" end_x="1" end_y="4"/>
<spine name="clk_rib_lvl2_x1y2_lower" start_x="1" start_y="2" end_x="1" end_y="0"/>
<spine name="clk_rib_lvl2_x2y2_upper" start_x="2" start_y="3" end_x="2" end_y="4"/>
<spine name="clk_rib_lvl2_x2y2_lower" start_x="2" start_y="2" end_x="2" end_y="0"/>
<spine name="clk_rib_lvl2_x3y2_upper" start_x="3" start_y="3" end_x="3" end_y="4"/>
<spine name="clk_rib_lvl2_x3y2_lower" start_x="3" start_y="2" end_x="3" end_y="0"/>
<spine name="clk_rib_lvl2_x4y2_upper" start_x="4" start_y="3" end_x="4" end_y="4"/>
<spine name="clk_rib_lvl2_x4y2_lower" start_x="4" start_y="2" end_x="4" end_y="0"/>
<taps>
<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
</taps>
</clock_network>
<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
<spine name="rst_spine_lvl0_botm0" start_x="1" start_y="1" end_x="1" end_y="2">
<switch_point tap="rst_spine_lvl1_right" x="1" y="2"/>
</spine>
<spine name="rst_spine_lvl0_botm1" start_x="2" start_y="1" end_x="2" end_y="2">
<switch_point tap="rst_spine_lvl1_left" x="2" y="2"/>
</spine>
<spine name="rst_spine_lvl1_left" start_x="2" start_y="2" end_x="0" end_y="2">
<switch_point tap="rst_rib_lvl2_x0y2_upper" x="0" y="2"/>
<switch_point tap="rst_rib_lvl2_x0y2_lower" x="0" y="2"/>
<switch_point tap="rst_rib_lvl2_x1y2_upper" x="1" y="2"/>
<switch_point tap="rst_rib_lvl2_x1y2_lower" x="1" y="2"/>
</spine>
<spine name="rst_spine_lvl1_right" start_x="2" start_y="2" end_x="4" end_y="2">
<switch_point tap="rst_rib_lvl2_x2y2_upper" x="2" y="2"/>
<switch_point tap="rst_rib_lvl2_x2y2_lower" x="2" y="2"/>
<switch_point tap="rst_rib_lvl2_x3y2_upper" x="3" y="2"/>
<switch_point tap="rst_rib_lvl2_x3y2_lower" x="3" y="2"/>
<switch_point tap="rst_rib_lvl2_x4y2_upper" x="4" y="2"/>
<switch_point tap="rst_rib_lvl2_x4y2_lower" x="4" y="2"/>
</spine>
<spine name="rst_rib_lvl2_x0y2_upper" start_x="0" start_y="3" end_x="0" end_y="4"/>
<spine name="rst_rib_lvl2_x0y2_lower" start_x="0" start_y="2" end_x="0" end_y="0"/>
<spine name="rst_rib_lvl2_x1y2_upper" start_x="1" start_y="3" end_x="1" end_y="4"/>
<spine name="rst_rib_lvl2_x1y2_lower" start_x="1" start_y="2" end_x="1" end_y="0"/>
<spine name="rst_rib_lvl2_x2y2_upper" start_x="2" start_y="3" end_x="2" end_y="4"/>
<spine name="rst_rib_lvl2_x2y2_lower" start_x="2" start_y="2" end_x="2" end_y="0"/>
<spine name="rst_rib_lvl2_x3y2_upper" start_x="3" start_y="3" end_x="3" end_y="4"/>
<spine name="rst_rib_lvl2_x3y2_lower" start_x="3" start_y="2" end_x="3" end_y="0"/>
<spine name="rst_rib_lvl2_x4y2_upper" start_x="4" start_y="3" end_x="4" end_y="4"/>
<spine name="rst_rib_lvl2_x4y2_lower" start_x="4" start_y="2" end_x="4" end_y="0"/>
<taps>
<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
</taps>
</clock_network>
</clock_networks>

8
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_reset.xml Normal file
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@ -0,0 +1,8 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="reset"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints>

8
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/pin_constraints_resetb.xml Normal file
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@ -0,0 +1,8 @@
<pin_constraints>
<!-- For a given .blif file, we want to assign
- the reset signal to the op_reset[0] port of the FPGA fabric
-->
<set_io pin="op_reset[0]" net="resetb" default_value="1"/>
<set_io pin="op_clk[0]" net="clk"/>
</pin_constraints>

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/repack_pin_constraints.xml Normal file
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@ -0,0 +1,4 @@
<repack_design_constraints>
<!-- Intended to be dummy -->
</repack_design_constraints>

54
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_3layer_2entry/config/task.conf Normal file
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@ -0,0 +1,54 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 3*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_clkntwk_no_ace_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_Ntwk1clk1rst2lvl_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_repack_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
openfpga_vpr_device_layout=4x4
openfpga_vpr_route_chan_width=32
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_3layer.xml
openfpga_verilog_testbench_port_mapping=--explicit_port_mapping
openfpga_route_clock_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
bench_yosys_dff_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = counter
bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_reset.xml
bench0_openfpga_verilog_testbench_port_mapping=
bench1_top = counter
bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_resetb.xml
bench1_openfpga_verilog_testbench_port_mapping=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=