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[core] code format

This commit is contained in:
tangxifan 2024-08-02 17:48:47 -07:00
parent 82cf7bbb8c
commit eeaa3373c6
4 changed files with 28 additions and 26 deletions
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12
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -548,7 +548,8 @@ static void add_rr_graph_block_clock_edges(
size_t curr_edge_count = edge_count;
for (RRNodeId des_node : find_clock_track2track_node(
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type,
chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir, verbose)) {
chan_coord, itree, ilvl, ClockTreePinId(ipin), node_dir,
verbose)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(
@ -606,7 +607,8 @@ static void try_find_and_add_clock_opin2track_node(
RRNodeId opin_node = rr_graph_view.node_lookup().find_node(
layer, grid_coord.x(), grid_coord.y(), OPIN, grid_pin_idx, pin_side);
if (rr_graph_view.valid_node(opin_node)) {
VTR_LOGV(verbose, "Connected OPIN '%s' to clock network\n", tap_pin_name.c_str());
VTR_LOGV(verbose, "Connected OPIN '%s' to clock network\n",
tap_pin_name.c_str());
opin_nodes.push_back(opin_node);
}
}
@ -704,9 +706,9 @@ static int add_rr_graph_opin2clk_edges(
vtr::Point<int> des_coord = clk_ntwk.spine_start_point(des_spine);
Direction des_spine_direction = clk_ntwk.spine_direction(des_spine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, ipin, des_spine_direction, verbose);
RRNodeId des_node = clk_rr_lookup.find_node(
des_coord.x(), des_coord.y(), clk_tree, des_spine_level, ipin,
des_spine_direction, verbose);
/* Walk through each qualified OPIN, build edges */
vtr::Point<int> src_coord =
clk_ntwk.spine_switch_point(ispine, switch_point_id);

30
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -108,12 +108,12 @@ static int route_clock_spine_switch_point(
Direction des_spine_direction = clk_ntwk.spine_direction(des_spine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, ipin, src_spine_direction, verbose);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, ipin, des_spine_direction, verbose);
RRNodeId src_node = clk_rr_lookup.find_node(src_coord.x(), src_coord.y(),
clk_tree, src_spine_level, ipin,
src_spine_direction, verbose);
RRNodeId des_node = clk_rr_lookup.find_node(des_coord.x(), des_coord.y(),
clk_tree, des_spine_level, ipin,
des_spine_direction, verbose);
VTR_ASSERT(rr_graph.valid_node(src_node));
VTR_ASSERT(rr_graph.valid_node(des_node));
/* Internal drivers may appear at the switch point. Check if there are
@ -200,9 +200,9 @@ static int route_spine_taps(
vtr::Point<int> src_coord = spine_coords[icoord];
Direction src_spine_direction = clk_ntwk.spine_direction(ispine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(ispine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, ipin, src_spine_direction, verbose);
RRNodeId src_node = clk_rr_lookup.find_node(
src_coord.x(), src_coord.y(), clk_tree, src_spine_level, ipin,
src_spine_direction, verbose);
for (RREdgeId edge : rr_graph.edge_range(src_node)) {
RRNodeId des_node = rr_graph.edge_sink_node(edge);
if (rr_graph.node_type(des_node) == IPIN) {
@ -389,12 +389,12 @@ static int rec_expand_and_route_clock_spine(
Direction des_spine_direction = clk_ntwk.spine_direction(curr_spine);
ClockLevelId src_spine_level = clk_ntwk.spine_level(curr_spine);
ClockLevelId des_spine_level = clk_ntwk.spine_level(curr_spine);
RRNodeId src_node =
clk_rr_lookup.find_node(src_coord.x(), src_coord.y(), clk_tree,
src_spine_level, curr_pin, src_spine_direction, verbose);
RRNodeId des_node =
clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree,
des_spine_level, curr_pin, des_spine_direction, verbose);
RRNodeId src_node = clk_rr_lookup.find_node(
src_coord.x(), src_coord.y(), clk_tree, src_spine_level, curr_pin,
src_spine_direction, verbose);
RRNodeId des_node = clk_rr_lookup.find_node(
des_coord.x(), des_coord.y(), clk_tree, des_spine_level, curr_pin,
des_spine_direction, verbose);
VTR_ASSERT(rr_graph.valid_node(src_node));
VTR_ASSERT(rr_graph.valid_node(des_node));
VTR_LOGV(verbose,

6
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1247,9 +1247,9 @@ static int build_top_module_global_net_from_tile_clock_arch_tree(
Direction entry_dir = clk_ntwk.spine_direction(spine);
t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine);
/* Find the routing resource node of the entry point */
RRNodeId entry_rr_node =
rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree,
clk_ntwk.spine_level(spine), pin, entry_dir, false);
RRNodeId entry_rr_node = rr_clock_lookup.find_node(
entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine),
pin, entry_dir, false);
/* Get the tile module and instance at the entry point */
const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate(

6
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -1282,9 +1282,9 @@ static int build_top_module_global_net_from_clock_arch_tree(
Direction entry_dir = clk_ntwk.spine_direction(spine);
t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine);
/* Find the routing resource node of the entry point */
RRNodeId entry_rr_node =
rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree,
clk_ntwk.spine_level(spine), pin, entry_dir, false);
RRNodeId entry_rr_node = rr_clock_lookup.find_node(
entry_point.x(), entry_point.y(), clk_tree, clk_ntwk.spine_level(spine),
pin, entry_dir, false);
/* Get the connection block module and instance at the entry point */
vtr::Point<size_t> entry_cb_coord(entry_point.x(), entry_point.y());