update code according to code review comments

docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst

@@ -521,3 +521,26 @@ write_fabric_pin_physical_location
   .. option:: --verbose
 
     Show verbose log
+
+.. _openfpga_setup_commands_report_reference:
+
+report_reference
+~~~~~~~~~~~~~~~~~~~~
+
+  Write reference information of each child module under a given parent module to a YAML file
+
+  .. option:: --file <string> or -f <string>
+
+    Specify the file name to write the reference information
+
+  .. option:: --module <string>
+
+    Specify the parent module name, under which the references of each child module will be reported.
+
+  .. option:: --no_time_stamp
+
+    Do not print time stamp in output files
+
+  .. option:: --verbose
+
+    Show verbose info

openfpga/src/base/openfpga_setup_command_template.h

@@ -1230,7 +1230,10 @@ void add_setup_command_templates(openfpga::Shell<T>& shell,
   /********************************
    * Command 'report_reference'
    */
+  /* The command should NOT be executed before 'build_fabric' */
   std::vector<ShellCommandId> cmd_dependency_report_reference;
+  cmd_dependency_write_fabric_pin_physical_location.push_back(
+    build_fabric_cmd_id);
   add_report_reference_command_template<T>(
     shell, openfpga_setup_cmd_class, cmd_dependency_report_reference, hidden);
 }

openfpga/src/utils/report_reference.cpp

@@ -16,6 +16,7 @@
 /* Headers from openfpgautil library */
 #include "command_exit_codes.h"
 #include "openfpga_digest.h"
+#include "openfpga_naming.h"
 #include "report_reference.h"
 
 /* begin namespace openfpga */
@@ -29,6 +30,54 @@ int report_reference(const char* fname, const std::string& module_name,
                      const bool& include_time_stamp, const bool& verbose) {
   vtr::ScopedStartFinishTimer timer("Report reference");
 
+  ModuleId parent_module = module_manager.find_module(module_name);
+  if (false == module_manager.valid_module_id(parent_module)) {
+    VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str());
+
+    if (verbose) write_module_to_file(fname, module_manager);
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  show_reference_count(parent_module, module_manager);
+
+  return write_reference_to_file(fname, parent_module, module_manager,
+                                 include_time_stamp, verbose);
+}
+
+/********************************************************************
+ * show reference count of each child module under given parent module
+ *******************************************************************/
+void show_reference_count(const ModuleId& parent_module,
+                          const ModuleManager& module_manager) {
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+  VTR_LOG(
+    "Module                                  Count                         \n");
+  VTR_LOG(
+    "--------------------------------------------------------------------- \n");
+  size_t ref_cnt = 0;
+  for (ModuleId child_module : module_manager.child_modules(parent_module)) {
+    std::string child_module_name = module_manager.module_name(child_module);
+    std::vector<size_t> child_inst_vec =
+      module_manager.child_module_instances(parent_module, child_module);
+    VTR_LOG("%-s   %d\n", child_module_name.c_str(), child_inst_vec.size());
+    ref_cnt += child_inst_vec.size();
+  }
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+  VTR_LOG("Total: %zu modules %zu references\n",
+          module_manager.child_modules(parent_module).size(), ref_cnt);
+  VTR_LOG(
+    "----------------------------------------------------------------------\n");
+}
+
+/********************************************************************
+ * write reference info to a given file in YAML format
+ *******************************************************************/
+int write_reference_to_file(const char* fname, const ModuleId& parent_module,
+                            const ModuleManager& module_manager,
+                            const bool& include_time_stamp,
+                            const bool& verbose) {
   std::fstream fp;
   fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
   openfpga::check_file_stream(fname, fp);
@@ -39,67 +88,76 @@ int report_reference(const char* fname, const std::string& module_name,
     fp << "Date: " << std::ctime(&end_time) << std::endl;
   }
 
-  ModuleId parent_module = module_manager.find_module(module_name);
-  if (ModuleId::INVALID() == parent_module) {
-    VTR_LOG_ERROR("Module %s doesn't exist\n", module_name.c_str());
-    return CMD_EXEC_MINOR_ERROR;
-  }
+  fp << "#the instance names are given during netlist generation" << std::endl;
 
-  if (module_manager.child_modules(parent_module).size() < 1) {
-    VTR_LOG_ERROR("Module %s contains no child module\n", module_name.c_str());
-    return CMD_EXEC_MINOR_ERROR;
-  }
-
-  VTR_LOG(
-    "--------------------------------------------------------------------------"
-    "----\n");
-  VTR_LOG(
-    "Module                                                         Reference "
-    "count\n");
-  VTR_LOG(
-    "--------------------------------------------------------------------------"
-    "----\n");
   size_t ref_cnt = 0;
-  for (ModuleId child_module : module_manager.child_modules(parent_module)) {
-    std::string child_module_name = module_manager.module_name(child_module);
-    std::vector<size_t> child_inst_vec =
-      module_manager.child_module_instances(parent_module, child_module);
-    VTR_LOG("%-s %d\n", child_module_name.c_str(), child_inst_vec.size());
-    ref_cnt += child_inst_vec.size();
-  }
-  VTR_LOG(
-    "--------------------------------------------------------------------------"
-    "----\n");
-  VTR_LOG("Total %zu modules %zu references\n",
-          module_manager.child_modules(parent_module).size(), ref_cnt);
-  VTR_LOG(
-    "--------------------------------------------------------------------------"
-    "----\n");
-
-  if (verbose) {
-    fp << "\nTotal " << module_manager.child_modules(parent_module).size()
-       << " modules " << ref_cnt << " references\n";
-  }
-
   fp << "references:" << std::endl;
   for (ModuleId child_module : module_manager.child_modules(parent_module)) {
     std::string child_module_name = module_manager.module_name(child_module);
     std::vector<size_t> child_inst_vec =
       module_manager.child_module_instances(parent_module, child_module);
-    fp << "- module: " << child_module_name.c_str() << "\n"
-       << "  reference count: " << child_inst_vec.size() << "\n"
-       << "  instances:"
-       << "\n";
+    fp << "- module: " << child_module_name.c_str() << std::endl
+       << "  count: " << child_inst_vec.size() << std::endl
+       << "  instances:" << std::endl;
     for (size_t inst_id : child_inst_vec) {
       std::string inst_name =
         module_manager.instance_name(parent_module, child_module, inst_id);
-      if (inst_name.size() > 0) fp << "    - " << inst_name.c_str() << "\n";
+      fp << "    - ";
+      if (true == inst_name.empty()) {
+        fp << generate_instance_name(child_module_name, inst_id) << std::endl;
+      } else {
+        fp << inst_name << std::endl;
+      }
     }
+    ref_cnt += child_inst_vec.size();
+  }
+
+  if (verbose) {
+    fp << std::endl
+       << "Total: " << module_manager.child_modules(parent_module).size()
+       << " modules " << ref_cnt << " references" << std::endl;
   }
 
   fp.close();
-
   return CMD_EXEC_SUCCESS;
 }
 
+/********************************************************************
+ * write all modules to a given file
+ *******************************************************************/
+void write_module_to_file(const char* fname,
+                          const ModuleManager& module_manager) {
+  std::fstream fp;
+  fp.open(std::string(fname), std::fstream::out | std::fstream::trunc);
+  openfpga::check_file_stream(fname, fp);
+
+  fp << "module_count: " << module_manager.modules().size() << std::endl;
+
+  for (ModuleId curr_module : module_manager.modules()) {
+    std::string curr_module_name = module_manager.module_name(curr_module);
+    fp << "module: " << curr_module_name.c_str() << std::endl;
+
+    for (ModuleId child_module : module_manager.child_modules(curr_module)) {
+      std::string child_module_name = module_manager.module_name(child_module);
+      std::vector<size_t> child_inst_vec =
+        module_manager.child_module_instances(curr_module, child_module);
+      fp << "  - child_module:" << child_module_name.c_str() << std::endl
+         << "    instance_count:" << child_inst_vec.size() << std::endl
+         << "    instances:" << std::endl;
+
+      for (size_t inst_id : child_inst_vec) {
+        std::string inst_name =
+          module_manager.instance_name(curr_module, child_module, inst_id);
+        fp << "      - ";
+        if (true == inst_name.empty()) {
+          fp << generate_instance_name(child_module_name, inst_id) << std::endl;
+        } else {
+          fp << inst_name << std::endl;
+        }
+      }
+    }
+  }
+  fp.close();
+}
+
 } /* end namespace openfpga */

openfpga/src/utils/report_reference.h

@@ -17,6 +17,17 @@ namespace openfpga {
 int report_reference(const char* fname, const std::string& module_name,
                      const ModuleManager& module_manager,
                      const bool& include_time_stamp, const bool& verbose);
+
+void show_reference_count(const ModuleId& parent_module,
+                          const ModuleManager& module_manager);
+
+int write_reference_to_file(const char* fname, const ModuleId& parent_module,
+                            const ModuleManager& module_manager,
+                            const bool& include_time_stamp,
+                            const bool& verbose);
+
+void write_module_to_file(const char* fname,
+                          const ModuleManager& module_manager);
 } /* end namespace openfpga */
 
 #endif

openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga

@@ -0,0 +1,35 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enabled frame view creation to save runtime and memory
+#    Note that this is turned on when bitstream generation 
+#    is the ONLY purpose of the flow!!!
+build_fabric --compress_routing --frame_view #--verbose
+
+# Report reference to a file
+report_reference ${OPENFPGA_REPORT_REFERENCE_OPTIONS}
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/tasks/basic_tests/report_reference/config/task.conf

@@ -0,0 +1,34 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/report_reference_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_report_reference_options=--file reference_info.yaml --module grid_io_right
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]