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[test] update golden outputs

This commit is contained in:
tangxifan 2024-07-08 23:24:16 -07:00
parent 092b8b038f
commit 5efc9d0e00
84 changed files with 15075 additions and 15075 deletions
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56
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31]
set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

840
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

@ -11,346 +11,6 @@
#############################################
set_units -time ns
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5
@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5
@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5

56
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,16 +6,24 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

256
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -197,18 +197,7 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
@ -243,8 +232,19 @@
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -267,67 +267,6 @@
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -423,34 +362,61 @@
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -485,19 +451,8 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
@ -515,16 +470,61 @@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

716
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
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File diff suppressed because it is too large Load Diff

14
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__0__0_ccff_tail));
@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__1__0_ccff_tail));
@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

120
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="83" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="84" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="56" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="57" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="58" mux_size="6">
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="222" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="222" index="21" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="59" mux_size="6">
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="224" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="224" index="23" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="60" mux_size="6">
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="61" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="62" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="63" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

132
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
View File

@ -1,90 +1,90 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="109" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="252" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="110" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="111" mux_size="6">
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="112" mux_size="6">
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="113" mux_size="6">
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="248" index="21" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="114" mux_size="6">
<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="249" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="250" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="249" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="250" index="23" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="115" mux_size="6">
<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="252" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="116" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="77" mux_size="6">
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="78" mux_size="6">
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="79" mux_size="6">
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="248" index="21" segment_id="0"/>
</IPIN>
</rr_cb>

120
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="6">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="23" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="6">
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

132
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
View File

@ -1,90 +1,90 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="6">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="23" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="6">
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
</rr_cb>

108
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -153,48 +153,44 @@ set_disable_timing gfpga_pad_GPIO_PAD[127]
set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -207,12 +203,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
@ -221,6 +221,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -231,6 +239,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -247,6 +257,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -255,32 +273,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -293,8 +295,6 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
##################################################
# Disable timing for Connection block cbx_1__0_
##################################################

6708
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

File diff suppressed because it is too large Load Diff

108
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,48 +6,44 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -60,12 +56,16 @@ set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logica
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
@ -74,6 +74,14 @@ set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -84,6 +92,8 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -100,6 +110,14 @@ set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_
set_disable_timing fpga_top/grid_clb_*__*_/logical_tile_clb_mode_clb__*/mem_fle_*_in_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
@ -108,32 +126,16 @@ set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -146,5 +148,3 @@ set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN

284
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -221,6 +221,8 @@
0
0
0
1
1
0
0
0
@ -621,6 +623,9 @@
0
0
0
1
1
1
0
0
0
@ -804,7 +809,6 @@
0
0
0
1
0
0
0
@ -828,8 +832,6 @@
0
0
0
1
1
0
0
0
@ -840,9 +842,7 @@
0
0
0
1
0
1
0
0
0
@ -864,7 +864,6 @@
0
0
0
1
0
0
0
@ -877,9 +876,6 @@
0
0
0
1
1
1
0
0
0
@ -898,6 +894,8 @@
0
0
0
1
1
0
0
0
@ -910,6 +908,7 @@
0
0
0
1
0
0
0
@ -922,13 +921,15 @@
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
@ -939,13 +940,9 @@
0
0
0
1
0
1
0
1
0
1
0
0
0
@ -975,6 +972,7 @@
0
0
0
1
0
0
0
@ -985,9 +983,13 @@
0
0
0
1
0
1
0
1
0
1
0
0
0
@ -1057,8 +1059,6 @@
0
0
0
1
1
0
0
0
@ -1075,6 +1075,7 @@
0
0
0
1
0
0
0
@ -1098,6 +1099,8 @@
0
0
0
1
1
0
0
0
@ -1108,7 +1111,9 @@
0
0
0
1
0
1
0
0
0
@ -1234,8 +1239,6 @@
0
0
0
1
1
0
0
0
@ -1263,9 +1266,7 @@
0
0
0
1
0
1
0
0
0
@ -1277,6 +1278,8 @@
0
0
0
1
1
0
0
0
@ -1723,9 +1726,6 @@
0
0
0
1
1
1
0
0
0
@ -1979,6 +1979,14 @@
0
0
0
1
1
1
0
0
0
0
0
0
0
0
@ -2360,7 +2368,7 @@
0
0
1
1
0
1
0
0
@ -2562,7 +2570,6 @@
0
0
0
1
0
0
0
@ -2593,6 +2600,15 @@
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
@ -2817,7 +2833,6 @@
0
0
0
1
1
0
0
@ -3054,6 +3069,9 @@
0
0
0
1
1
1
0
0
0
@ -3552,6 +3570,10 @@
0
0
0
0
0
0
0
1
1
1
@ -3779,7 +3801,78 @@
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
@ -3819,24 +3912,6 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -3858,12 +3933,22 @@
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3899,18 +3984,8 @@
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3944,6 +4019,14 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
@ -3987,14 +4070,7 @@
0
0
0
1
1
1
1
1
1
0
1
0
0
0
@ -4024,6 +4100,11 @@
1
1
1
1
1
1
1
1
0
0
0
@ -4071,21 +4152,6 @@
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
@ -4133,8 +4199,6 @@
0
0
0
1
1
0
0
0
@ -4147,67 +4211,3 @@
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

8124
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fabric_bitstream.xml
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File diff suppressed because it is too large Load Diff

104
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -807,7 +807,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__0_ccff_tail),
.ccff_head(grid_io_top_1_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -829,7 +829,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__1_ccff_tail),
.ccff_head(grid_io_top_2_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -851,7 +851,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__2_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__2_ccff_tail),
.ccff_head(grid_io_top_3_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -873,7 +873,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__4__3_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__4__3_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -983,7 +983,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__3_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_1_ccff_tail),
.ccff_head(cbx_1__0__3_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1005,7 +1005,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__2_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_2_ccff_tail),
.ccff_head(cbx_1__0__2_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1027,7 +1027,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_3_ccff_tail),
.ccff_head(cbx_1__0__1_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1049,7 +1049,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -1538,7 +1538,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_1_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:9]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -1568,7 +1568,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_2_ccff_tail),
.ccff_head(grid_io_left_1_ccff_tail),
.chany_top_out(sb_0__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]),
@ -1599,7 +1599,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_1_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_3_ccff_tail),
.ccff_head(grid_io_left_2_ccff_tail),
.chany_top_out(sb_0__1__1_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__1_chany_bottom_out[0:9]),
@ -1630,7 +1630,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_2_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__4__0_ccff_tail),
.ccff_head(grid_io_left_3_ccff_tail),
.chany_top_out(sb_0__1__2_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__2_chany_bottom_out[0:9]),
@ -1688,7 +1688,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_3_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__0_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:9]),
@ -1719,7 +1719,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_2_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_0_ccff_tail),
.ccff_head(grid_io_bottom_3_ccff_tail),
.chany_top_out(sb_1__0__1_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__1_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__1_chanx_left_out[0:9]),
@ -1750,7 +1750,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_4_ccff_tail),
.ccff_head(grid_io_bottom_2_ccff_tail),
.chany_top_out(sb_1__0__2_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__2_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__2_chanx_left_out[0:9]),
@ -1770,7 +1770,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__0_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_5_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_top_out(sb_1__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]),
@ -1791,7 +1791,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__1_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_2_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_1_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_1_ccff_tail),
.ccff_head(grid_clb_5_ccff_tail),
.chany_top_out(sb_1__1__1_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__1_chany_bottom_out[0:9]),
@ -1812,7 +1812,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__2_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_2_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_7_ccff_tail),
.ccff_head(grid_clb_1_ccff_tail),
.chany_top_out(sb_1__1__2_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__2_chany_bottom_out[0:9]),
@ -1833,7 +1833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__3_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_5_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_4_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_9_ccff_tail),
.ccff_head(grid_clb_0_ccff_tail),
.chany_top_out(sb_1__1__3_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__3_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__3_chany_bottom_out[0:9]),
@ -1854,7 +1854,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__4_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_6_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_5_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_2_ccff_tail),
.ccff_head(grid_clb_9_ccff_tail),
.chany_top_out(sb_1__1__4_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__4_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__4_chany_bottom_out[0:9]),
@ -1875,7 +1875,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__5_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_7_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_6_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_11_ccff_tail),
.ccff_head(grid_clb_2_ccff_tail),
.chany_top_out(sb_1__1__5_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__5_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__5_chany_bottom_out[0:9]),
@ -1896,7 +1896,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__6_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_9_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_8_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_13_ccff_tail),
.ccff_head(grid_clb_4_ccff_tail),
.chany_top_out(sb_1__1__6_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__6_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__6_chany_bottom_out[0:9]),
@ -1917,7 +1917,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__7_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_10_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_9_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_6_ccff_tail),
.ccff_head(grid_clb_13_ccff_tail),
.chany_top_out(sb_1__1__7_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__7_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__7_chany_bottom_out[0:9]),
@ -1938,7 +1938,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__8_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_11_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_10_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_15_ccff_tail),
.ccff_head(grid_clb_6_ccff_tail),
.chany_top_out(sb_1__1__8_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__8_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__8_chany_bottom_out[0:9]),
@ -1970,7 +1970,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_3_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_1_ccff_tail),
.ccff_head(grid_clb_7_ccff_tail),
.chanx_right_out(sb_1__4__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__0_chanx_left_out[0:9]),
@ -2001,7 +2001,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_7_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_2_ccff_tail),
.ccff_head(grid_clb_11_ccff_tail),
.chanx_right_out(sb_1__4__1_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__1_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__1_chanx_left_out[0:9]),
@ -2032,7 +2032,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_2_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_11_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_top_3_ccff_tail),
.ccff_head(grid_clb_15_ccff_tail),
.chanx_right_out(sb_1__4__2_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__4__2_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__4__2_chanx_left_out[0:9]),
@ -2060,7 +2060,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_8_ccff_tail),
.ccff_head(grid_io_bottom_1_ccff_tail),
.chany_top_out(sb_4__0__0_chany_top_out[0:9]),
.chanx_left_out(sb_4__0__0_chanx_left_out[0:9]),
.ccff_tail(sb_4__0__0_ccff_tail));
@ -2090,7 +2090,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__9_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_13_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_12_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_12_ccff_tail),
.ccff_head(grid_clb_8_ccff_tail),
.chany_top_out(sb_4__1__0_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__0_chanx_left_out[0:9]),
@ -2121,7 +2121,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__10_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_14_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_13_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_10_ccff_tail),
.ccff_head(grid_clb_12_ccff_tail),
.chany_top_out(sb_4__1__1_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__1_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__1_chanx_left_out[0:9]),
@ -2152,7 +2152,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.chanx_left_in(cbx_1__1__11_chanx_right_out[0:9]),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_(grid_clb_15_bottom_width_0_height_0_subtile_0__pin_O_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_14_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_clb_14_ccff_tail),
.ccff_head(grid_clb_10_ccff_tail),
.chany_top_out(sb_4__1__2_chany_top_out[0:9]),
.chany_bottom_out(sb_4__1__2_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__1__2_chanx_left_out[0:9]),
@ -2180,7 +2180,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_3_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_15_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_clb_14_ccff_tail),
.chany_bottom_out(sb_4__4__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_4__4__0_chanx_left_out[0:9]),
.ccff_tail(sb_4__4__0_ccff_tail));
@ -2529,7 +2529,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:9]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2548,7 +2548,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__0_chany_top_out[0:9]),
.chany_top_in(sb_0__1__1_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(sb_0__1__1_ccff_tail),
.chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2567,7 +2567,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__1_chany_top_out[0:9]),
.chany_top_in(sb_0__1__2_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__1_ccff_tail),
.ccff_head(sb_0__1__2_ccff_tail),
.chany_bottom_out(cby_0__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2586,7 +2586,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__2_chany_top_out[0:9]),
.chany_top_in(sb_0__4__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__2_ccff_tail),
.ccff_head(sb_0__4__0_ccff_tail),
.chany_bottom_out(cby_0__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2605,7 +2605,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:9]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2619,7 +2619,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__0_chany_top_out[0:9]),
.chany_top_in(sb_1__1__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(cbx_1__1__1_ccff_tail),
.chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2633,7 +2633,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__1_chany_top_out[0:9]),
.chany_top_in(sb_1__1__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__1_ccff_tail),
.ccff_head(cbx_1__1__2_ccff_tail),
.chany_bottom_out(cby_1__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__2_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2647,7 +2647,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__2_chany_top_out[0:9]),
.chany_top_in(sb_1__4__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__2_ccff_tail),
.ccff_head(cbx_1__4__0_ccff_tail),
.chany_bottom_out(cby_1__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__3_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2661,7 +2661,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__1_chany_top_out[0:9]),
.chany_top_in(sb_1__1__3_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__1_ccff_tail),
.ccff_head(cbx_1__1__3_ccff_tail),
.chany_bottom_out(cby_1__1__4_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__4_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__4_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2675,7 +2675,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__3_chany_top_out[0:9]),
.chany_top_in(sb_1__1__4_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__3_ccff_tail),
.ccff_head(cbx_1__1__4_ccff_tail),
.chany_bottom_out(cby_1__1__5_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__5_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__5_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2689,7 +2689,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__4_chany_top_out[0:9]),
.chany_top_in(sb_1__1__5_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__4_ccff_tail),
.ccff_head(cbx_1__1__5_ccff_tail),
.chany_bottom_out(cby_1__1__6_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__6_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__6_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2703,7 +2703,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__5_chany_top_out[0:9]),
.chany_top_in(sb_1__4__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__5_ccff_tail),
.ccff_head(cbx_1__4__1_ccff_tail),
.chany_bottom_out(cby_1__1__7_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__7_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__7_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2717,7 +2717,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__2_chany_top_out[0:9]),
.chany_top_in(sb_1__1__6_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__2_ccff_tail),
.ccff_head(cbx_1__1__6_ccff_tail),
.chany_bottom_out(cby_1__1__8_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__8_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__8_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2731,7 +2731,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__6_chany_top_out[0:9]),
.chany_top_in(sb_1__1__7_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__6_ccff_tail),
.ccff_head(cbx_1__1__7_ccff_tail),
.chany_bottom_out(cby_1__1__9_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__9_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__9_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2745,7 +2745,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__7_chany_top_out[0:9]),
.chany_top_in(sb_1__1__8_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__7_ccff_tail),
.ccff_head(cbx_1__1__8_ccff_tail),
.chany_bottom_out(cby_1__1__10_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__10_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__10_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2759,7 +2759,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__8_chany_top_out[0:9]),
.chany_top_in(sb_1__4__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__8_ccff_tail),
.ccff_head(cbx_1__4__2_ccff_tail),
.chany_bottom_out(cby_1__1__11_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__11_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_1__1__11_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -2773,7 +2773,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__0__0_chany_top_out[0:9]),
.chany_top_in(sb_4__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__3_ccff_tail),
.ccff_head(cbx_1__1__9_ccff_tail),
.chany_bottom_out(cby_4__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2793,7 +2793,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__0_chany_top_out[0:9]),
.chany_top_in(sb_4__1__1_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__9_ccff_tail),
.ccff_head(cbx_1__1__10_ccff_tail),
.chany_bottom_out(cby_4__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2813,7 +2813,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__1_chany_top_out[0:9]),
.chany_top_in(sb_4__1__2_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__10_ccff_tail),
.ccff_head(cbx_1__1__11_ccff_tail),
.chany_bottom_out(cby_4__1__2_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__2_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__2_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -2833,7 +2833,7 @@ wire [0:9] sb_4__4__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_4__1__2_chany_top_out[0:9]),
.chany_top_in(sb_4__4__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__11_ccff_tail),
.ccff_head(cbx_1__4__3_ccff_tail),
.chany_bottom_out(cby_4__1__3_chany_bottom_out[0:9]),
.chany_top_out(cby_4__1__3_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_4__1__3_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,60 +1,60 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="179" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="180" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="152" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="153" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1055" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1055" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="154" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="155" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1039" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="156" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="157" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1052" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="158" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1055" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1044" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1055" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="159" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1047" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1056" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

76
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml
View File

@ -1,60 +1,60 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="327" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="328" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="300" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="301" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="302" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="303" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1041" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="304" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="305" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1050" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="306" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1057" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1042" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1057" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="307" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1049" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1054" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="475" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="476" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="448" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1067" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1067" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="449" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1065" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1068" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1065" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1068" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="450" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1066" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1069" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1066" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1069" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="451" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1064" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1043" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="452" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="453" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1048" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1067" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1048" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1067" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="454" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1040" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1065" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1068" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1063" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1040" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1065" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1068" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1063" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="455" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1066" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1051" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1062" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1069" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1066" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1051" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1062" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1069" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_0__4_.xml
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@ -1,60 +1,60 @@
<rr_cb x="0" y="4" num_sides="4">
<IPIN side="right" index="0" node_id="623" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1070" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1066" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1070" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1066" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="624" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1064" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1064" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="596" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1065" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1073" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1065" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1073" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="597" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1071" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1074" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1069" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1071" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1074" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1069" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="598" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1072" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1068" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1075" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1072" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1068" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1075" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="599" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1070" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1045" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1066" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1061" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1070" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1045" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1066" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1061" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="600" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1064" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1059" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1060" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1067" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1064" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1059" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1060" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1067" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="601" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1058" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1065" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1046" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1073" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1058" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1065" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1046" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1073" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="602" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1038" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1071" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1074" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1069" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1038" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1071" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1074" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1069" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="603" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1072" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1053" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1068" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1075" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1072" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1053" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1068" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1075" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="200" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1076" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1077" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1086" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1087" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1076" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1077" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1086" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1087" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="201" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1078" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1079" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1078" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1079" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="173" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1080" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1081" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1090" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1091" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1080" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1081" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1090" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1091" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="174" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1082" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1083" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1082" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1083" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="175" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1084" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1085" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1084" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1085" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="348" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1096" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1079" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1084" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1089" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1096" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1079" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1084" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1089" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="349" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1076" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1081" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1076" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1081" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="321" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1078" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1083" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1088" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1099" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1078" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1083" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1088" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1099" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="322" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1080" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1097" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1080" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1097" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="323" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1098" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1087" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1098" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1087" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="1" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="496" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1102" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1081" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1098" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1091" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1102" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1081" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1098" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1091" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="497" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1096" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1083" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1096" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1083" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="469" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1076" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1097" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1086" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1105" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1076" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1097" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1086" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1105" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="470" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1078" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1103" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1078" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1103" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="471" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1104" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1089" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1104" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1089" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="1" y="4" num_sides="4">
<IPIN side="right" index="0" node_id="644" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1108" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1083" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1104" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1099" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1108" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1083" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1104" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1099" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="645" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1102" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1097" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1102" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1097" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="617" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1096" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1103" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1084" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1111" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1096" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1103" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1084" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1111" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="618" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1076" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1109" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1076" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1109" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="619" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1110" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1091" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1110" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1091" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="2" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="221" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1114" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1115" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1124" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1125" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1114" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1115" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1124" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1125" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="222" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1116" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1117" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1116" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1117" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="194" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1118" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1119" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1128" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1129" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1118" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1119" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1128" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1129" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="195" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1120" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1121" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1120" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1121" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="196" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1122" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1123" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1122" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1123" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_2__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="2" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="369" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1134" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1117" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1122" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1127" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1134" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1117" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1122" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1127" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="370" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1114" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1119" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1114" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1119" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="342" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1116" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1121" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1126" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1137" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1116" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1121" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1126" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1137" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="343" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1118" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1135" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1118" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1135" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="344" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1136" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1125" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1136" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1125" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="2" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="517" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1140" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1119" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1136" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1129" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1140" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1119" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1136" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1129" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="518" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1134" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1121" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1134" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1121" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="490" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1114" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1135" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1124" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1143" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1114" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1135" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1124" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1143" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="491" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1116" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1141" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1116" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1141" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="492" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1142" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1127" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1142" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1127" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="2" y="4" num_sides="4">
<IPIN side="right" index="0" node_id="665" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1146" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1121" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1142" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1137" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1146" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1121" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1142" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1137" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="666" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1140" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1135" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1140" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1135" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="638" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1134" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1141" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1122" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1149" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1134" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1141" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1122" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1149" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="639" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1114" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1147" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1114" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1147" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="640" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1148" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1129" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1148" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1129" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="3" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="242" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1152" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1153" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1162" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1163" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1152" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1153" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1162" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1163" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="243" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1154" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1155" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1154" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1155" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="215" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1156" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1157" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1166" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1167" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1156" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1157" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1166" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1167" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="216" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1158" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1159" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1158" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1159" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="217" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1160" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1161" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1160" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1161" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="3" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="390" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1172" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1155" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1160" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1165" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1172" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1155" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1160" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1165" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="391" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1152" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1157" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1152" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1157" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="363" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1154" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1159" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1164" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1175" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1154" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1159" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1164" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1175" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="364" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1156" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1173" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1156" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1173" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="365" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1174" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1163" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1174" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1163" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml/cby_3__3_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="538" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1178" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1157" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1174" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1167" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1178" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1157" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1174" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1167" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="539" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1172" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1159" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1172" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1159" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="511" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1152" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1173" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1162" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1181" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1152" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1173" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1162" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1181" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="512" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1154" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1179" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1154" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1179" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="513" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1180" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1165" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1180" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1165" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,26 +1,26 @@
<rr_cb x="3" y="4" num_sides="4">
<IPIN side="right" index="0" node_id="686" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1184" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1159" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1180" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1175" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1184" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1159" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1180" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1175" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="687" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1178" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1173" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1178" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1173" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="659" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1172" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1179" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1160" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1187" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1172" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1179" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1160" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1187" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="660" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1152" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1185" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1152" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1185" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="661" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1186" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1167" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1186" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1167" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="268" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1191" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1201" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1191" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1201" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="269" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1193" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1202" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1203" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1193" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1202" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1203" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="270" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1194" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1204" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1194" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1204" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="271" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1196" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1206" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1207" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1196" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1206" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1207" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="272" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1198" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1199" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1208" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1209" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1199" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1208" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1209" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="273" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1191" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1201" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1191" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1201" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="274" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1193" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1202" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1203" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1193" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1202" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1203" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="275" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1194" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1204" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1194" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1204" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="236" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1196" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1206" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1207" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1196" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1206" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1207" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="237" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1208" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1209" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1208" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1209" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="238" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1191" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1191" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="416" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1193" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1203" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1193" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1203" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="417" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="418" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1202" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1202" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="419" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1194" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1214" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1209" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1194" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1214" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1209" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="420" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1212" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1201" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1206" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1215" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1212" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1201" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1206" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1215" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="421" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1193" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1203" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1193" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1203" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="422" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="423" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1202" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1202" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="384" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1194" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1214" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1209" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1194" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1214" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1209" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="385" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1206" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1215" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1206" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1215" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="386" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1193" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1193" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="3" num_sides="4">
<IPIN side="right" index="0" node_id="564" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1212" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1212" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="565" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="566" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1219" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1219" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="567" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1217" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1220" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1215" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1217" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1220" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1215" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="568" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1218" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1203" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1214" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1221" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1218" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1203" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1214" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1221" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="569" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1212" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1212" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="570" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="571" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1200" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1219" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1200" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1219" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="532" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1192" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1217" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1220" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1215" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1192" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1217" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1220" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1215" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="533" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1214" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1221" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1214" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1221" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="534" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1195" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1216" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1195" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,64 +1,64 @@
<rr_cb x="4" y="4" num_sides="4">
<IPIN side="right" index="0" node_id="712" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1218" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1218" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="713" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1216" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1212" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1219" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1216" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1212" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1219" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="714" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1217" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1225" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1217" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1225" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="715" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1223" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1226" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1221" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1223" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1226" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1221" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="716" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1224" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1205" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1220" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1227" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1224" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1205" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1220" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1227" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="717" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1218" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1213" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1218" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1213" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="718" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1216" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1211" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1212" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1219" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1216" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1211" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1212" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1219" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="719" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1210" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1217" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1198" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1225" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1210" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1217" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1198" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1225" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="680" mux_size="4">
<driver_node type="CHANY" side="top" node_id="1190" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1223" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1226" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1221" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1190" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1223" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1226" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1221" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="681" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1220" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1227" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1220" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1227" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="682" mux_size="2">
<driver_node type="CHANY" side="top" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="1197" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1222" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="1197" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,60 +1,60 @@
<rr_cb x="0" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__3_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__4_.xml
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@ -1,26 +1,26 @@
<rr_cb x="1" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__1_.xml
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@ -1,26 +1,26 @@
<rr_cb x="2" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="2" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__3_.xml
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@ -1,26 +1,26 @@
<rr_cb x="2" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__4_.xml
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@ -1,26 +1,26 @@
<rr_cb x="2" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__1_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__2_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__3_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

28
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_3__4_.xml
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@ -1,26 +1,26 @@
<rr_cb x="3" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__1_.xml
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@ -1,64 +1,64 @@
<rr_cb x="4" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

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openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__2_.xml
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@ -1,64 +1,64 @@
<rr_cb x="4" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

80
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__3_.xml
View File

@ -1,64 +1,64 @@
<rr_cb x="4" y="3" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

80
openfpga_flow/tasks/basic_tests/no_time_stamp/device_4x4/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_4__4_.xml
View File

@ -1,64 +1,64 @@
<rr_cb x="4" y="4" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="2">
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="2">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
</IPIN>
</rr_cb>

56
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -57,16 +57,24 @@ set_disable_timing gfpga_pad_GPIO_PAD[31]
set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -77,6 +85,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -91,30 +103,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

840
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

@ -11,346 +11,6 @@
#############################################
set_units -time ns
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_0__0_/mem_top_track_0/DFF_2_/D 5
@ -465,84 +125,8 @@ set_max_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/s
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__0_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_0_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__0_/mem_top_track_0/DFF_1_/Q -to fpga_top/sb_1__0_/mem_top_track_0/DFF_2_/D 5
@ -725,8 +309,424 @@ set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__0_/mem_top_ipin_7/DFF_2_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_bottom_1__0_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_top_1__2_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_0/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_2/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_4/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_6/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_8/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_10/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_12/DFF_2_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_14/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_16/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_18/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_20/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_22/DFF_1_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_0_/Q -to fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_right_track_24/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_3/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_15/DFF_2_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_0__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_left_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_0/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_1/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_2/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_3/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_4/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_5/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_6/DFF_2_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_0_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_1_/Q -to fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/cby_0__1_/mem_right_ipin_7/DFF_2_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__5/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/D 2.5
set_max_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/grid_io_left_0__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/GPIO_DFF_mem/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_bottom_track_25/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_1/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_3/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_5/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_7/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_9/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_11/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_13/DFF_2_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_15/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_17/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_19/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_21/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_23/DFF_1_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_0_/Q -to fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/D 2.5
set_max_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/sb_1__1_/mem_left_track_25/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_2/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_3/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_4/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_5/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_6/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_bottom_ipin_7/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_0/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_1/DFF_2_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_0_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_1_/Q -to fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/D 2.5
set_max_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 5
set_min_delay -from fpga_top/cbx_1__1_/mem_top_ipin_2/DFF_2_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 5
set_min_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_0_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/D 2.5
set_max_delay -from fpga_top/cby_1__1_/mem_left_ipin_0/DFF_1_/Q -to fpga_top/cby_1__1_/mem_left_ipin_0/DFF_2_/D 5

56
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,16 +6,24 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
@ -26,6 +34,10 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
@ -40,30 +52,18 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFF_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFF_mem/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFF_*_/Q

256
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -197,18 +197,7 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
@ -243,8 +232,19 @@
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -267,67 +267,6 @@
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -423,34 +362,61 @@
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
@ -485,19 +451,8 @@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
@ -515,16 +470,61 @@
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

716
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fabric_bitstream.xml
View File

File diff suppressed because it is too large Load Diff

14
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -162,7 +162,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__1__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -206,7 +206,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -284,7 +284,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:12]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:12]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -338,7 +338,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:12]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__0__0_ccff_tail));
@ -365,7 +365,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_(grid_clb_0_top_width_0_height_0_subtile_0__pin_O_2_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:12]),
.chanx_left_out(sb_1__1__0_chanx_left_out[0:12]),
.ccff_tail(sb_1__1__0_ccff_tail));
@ -414,7 +414,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:12]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:12]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_0__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_I_3_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_I_3_),
@ -433,7 +433,7 @@ wire [0:12] sb_1__1__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:12]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:12]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:12]),
.chany_top_out(cby_1__1__0_chany_top_out[0:12]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

120
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="83" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="84" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="56" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="57" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="58" mux_size="6">
<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="222" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="207" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="208" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="221" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="222" index="21" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="59" mux_size="6">
<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="224" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="209" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="210" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="223" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="224" index="23" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="60" mux_size="6">
<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="211" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="212" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="225" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="226" index="25" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="61" mux_size="6">
<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="201" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="202" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="213" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="214" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="62" mux_size="6">
<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="203" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="204" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="215" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="216" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="63" mux_size="6">
<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="205" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="206" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="217" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="218" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="219" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="220" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

132
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
View File

@ -1,90 +1,90 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="109" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="252" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="110" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="111" mux_size="6">
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="112" mux_size="6">
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="113" mux_size="6">
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="248" index="21" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="114" mux_size="6">
<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="249" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="250" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="235" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="236" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="249" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="250" index="23" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="115" mux_size="6">
<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="237" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="238" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="251" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="252" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="116" mux_size="6">
<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="227" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="228" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="239" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="240" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="77" mux_size="6">
<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="229" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="230" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="241" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="242" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="78" mux_size="6">
<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="231" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="232" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="243" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="244" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="79" mux_size="6">
<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="233" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="234" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="245" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="246" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="247" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="248" index="21" segment_id="0"/>
</IPIN>
</rr_cb>

120
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
View File

@ -1,82 +1,82 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="6">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="23" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="6">
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
</rr_cb>

132
openfpga_flow/tasks/basic_tests/no_time_stamp/dump_waveform/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
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@ -1,90 +1,90 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="6">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="22" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="23" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="6">
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="24" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="25" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="6">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="6">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="6">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="6">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="20" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="21" segment_id="0"/>
</IPIN>
</rr_cb>

124
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -90,58 +90,6 @@ set_disable_timing set[0]
set_disable_timing reset[0]
set_disable_timing pReset[0]
set_disable_timing prog_clk[0]
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
@ -168,6 +116,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
@ -186,6 +190,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
@ -194,24 +202,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
@ -220,6 +218,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q

3092
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/ccff_timing.sdc
View File

File diff suppressed because it is too large Load Diff

124
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/disable_configurable_memory_outputs.sdc
View File

@ -6,58 +6,6 @@
# Organization: University of Utah
#############################################
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
@ -84,6 +32,62 @@ set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_top_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_bottom_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_right_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_top_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/Q
set_disable_timing fpga_top/grid_io_left_*__*_/logical_tile_io_mode_io__*/logical_tile_io_mode_physical__iopad_*/GPIO_DFFR_mem/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
@ -102,6 +106,10 @@ set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
@ -110,24 +118,14 @@ set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_left_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cby_*__*_/mem_right_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/Q
set_disable_timing fpga_top/cbx_*__*_/mem_bottom_ipin_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_top_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_right_track_*/DFFR_*_/Q
@ -136,6 +134,8 @@ set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_bottom_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/QN
set_disable_timing fpga_top/sb_*__*_/mem_left_track_*/DFFR_*_/Q

266
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -339,13 +339,13 @@
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
@ -357,11 +357,13 @@
0
0
0
1
0
0
0
1
0
0
1
0
0
0
@ -375,21 +377,21 @@
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
@ -397,7 +399,7 @@
0
0
0
1
0
0
1
0
@ -407,7 +409,7 @@
0
0
0
1
0
0
0
0
@ -421,7 +423,7 @@
0
0
0
1
0
0
1
0
@ -429,10 +431,14 @@
0
0
0
1
0
0
0
1
0
1
0
0
0
0
@ -445,7 +451,7 @@
0
0
0
1
0
0
1
0
@ -827,19 +833,19 @@
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
@ -863,11 +869,11 @@
0
0
0
1
0
0
0
1
0
1
0
1
0
@ -877,7 +883,6 @@
0
0
0
1
0
0
0
@ -885,15 +890,15 @@
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
0
0
@ -904,16 +909,11 @@
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
@ -1297,26 +1297,20 @@
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
@ -1345,6 +1339,7 @@
0
0
0
1
0
0
0
@ -1352,6 +1347,7 @@
0
0
0
1
0
0
0
@ -1359,6 +1355,7 @@
0
0
0
1
0
0
0
@ -1366,13 +1363,7 @@
0
0
0
0
0
0
0
0
0
0
1
0
0
0
@ -1390,10 +1381,9 @@
0
0
0
1
0
0
0
0
1
0
0
0
@ -1735,25 +1725,21 @@
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
@ -1765,6 +1751,8 @@
0
0
0
0
0
1
0
0
@ -1773,15 +1761,15 @@
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
@ -1789,11 +1777,13 @@
0
0
0
1
0
0
0
0
0
1
0
1
0
@ -1811,13 +1801,13 @@
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
@ -1841,15 +1831,23 @@
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
@ -1868,14 +1866,6 @@
0
0
1
1
1
1
1
1
1
1
1
0
0
0
@ -1909,7 +1899,7 @@
0
0
0
0
1
0
1
0
@ -1917,13 +1907,12 @@
0
0
0
1
0
0
1
0
0
0
1
0
0
0
@ -1934,16 +1923,19 @@
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
@ -1951,13 +1943,19 @@
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
@ -2027,13 +2025,10 @@
0
0
0
1
0
0
0
1
0
1
0
0
0
@ -2041,7 +2036,6 @@
0
0
0
1
0
0
0
@ -2055,12 +2049,54 @@
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
@ -2073,31 +2109,41 @@
0
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
@ -2127,38 +2173,38 @@
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
@ -2187,7 +2233,7 @@
0
0
0
1
0
0
1
0
@ -2195,6 +2241,10 @@
0
0
0
1
0
0
0
0
0
1
@ -2221,17 +2271,15 @@
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
0
@ -2250,38 +2298,28 @@
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
@ -2293,13 +2331,9 @@
0
0
0
0
0
1
0
1
0
1
0
0
0
@ -2317,8 +2351,6 @@
0
0
0
1
1
0
0
0
@ -2341,35 +2373,3 @@
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

3308
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fabric_bitstream.xml
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File diff suppressed because it is too large Load Diff

36
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/fpga_top.v
View File

@ -359,7 +359,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__0_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__2__0_ccff_tail),
.ccff_head(grid_io_top_1_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -382,7 +382,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.bottom_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_),
.bottom_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_),
.bottom_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__2__1_top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(cbx_1__2__1_ccff_tail),
.ccff_head(grid_io_right_0_ccff_tail),
.bottom_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_0__pin_inpad_0_),
.bottom_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_1__pin_inpad_0_),
.bottom_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_2__pin_inpad_0_),
@ -451,7 +451,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(grid_io_bottom_1_ccff_tail),
.ccff_head(cbx_1__0__1_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -474,7 +474,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.top_width_0_height_0_subtile_5__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_),
.top_width_0_height_0_subtile_6__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_),
.top_width_0_height_0_subtile_7__pin_outpad_0_(cbx_1__0__0_bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_),
.ccff_head(ccff_head),
.ccff_head(cbx_1__0__0_ccff_tail),
.top_width_0_height_0_subtile_0__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_0__pin_inpad_0_),
.top_width_0_height_0_subtile_1__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_1__pin_inpad_0_),
.top_width_0_height_0_subtile_2__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_2__pin_inpad_0_),
@ -684,7 +684,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.right_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_),
.right_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_1_ccff_tail),
.ccff_head(ccff_head),
.chany_top_out(sb_0__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__0__0_chanx_right_out[0:9]),
.ccff_tail(sb_0__0__0_ccff_tail));
@ -715,7 +715,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_5__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_6__pin_inpad_0_),
.bottom_left_grid_right_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_left_0_right_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(sb_0__2__0_ccff_tail),
.ccff_head(grid_io_left_1_ccff_tail),
.chany_top_out(sb_0__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_0__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_0__1__0_chany_bottom_out[0:9]),
@ -781,7 +781,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_1_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_left_0_ccff_tail),
.ccff_head(sb_0__0__0_ccff_tail),
.chany_top_out(sb_1__0__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__0__0_chanx_right_out[0:9]),
.chanx_left_out(sb_1__0__0_chanx_left_out[0:9]),
@ -810,7 +810,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_5_),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_6_),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_1_bottom_width_0_height_0_subtile_0__pin_O_7_),
.ccff_head(grid_clb_3_ccff_tail),
.ccff_head(grid_io_left_0_ccff_tail),
.chany_top_out(sb_1__1__0_chany_top_out[0:9]),
.chanx_right_out(sb_1__1__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__1__0_chany_bottom_out[0:9]),
@ -843,7 +843,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_0_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_top_1_ccff_tail),
.ccff_head(grid_clb_3_ccff_tail),
.chanx_right_out(sb_1__2__0_chanx_right_out[0:9]),
.chany_bottom_out(sb_1__2__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_1__2__0_chanx_left_out[0:9]),
@ -878,7 +878,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_bottom_grid_top_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_5__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_6__pin_inpad_0_),
.left_bottom_grid_top_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_bottom_0_top_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_clb_0_ccff_tail),
.ccff_head(grid_io_bottom_1_ccff_tail),
.chany_top_out(sb_2__0__0_chany_top_out[0:9]),
.chanx_left_out(sb_2__0__0_chanx_left_out[0:9]),
.ccff_tail(sb_2__0__0_ccff_tail));
@ -917,7 +917,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_5_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_5_),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_6_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_6_),
.left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_7_(grid_clb_3_bottom_width_0_height_0_subtile_0__pin_O_7_),
.ccff_head(grid_clb_2_ccff_tail),
.ccff_head(grid_clb_0_ccff_tail),
.chany_top_out(sb_2__1__0_chany_top_out[0:9]),
.chany_bottom_out(sb_2__1__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_2__1__0_chanx_left_out[0:9]),
@ -948,7 +948,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.left_top_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_5__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_6__pin_inpad_0_),
.left_top_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_(grid_io_top_1_bottom_width_0_height_0_subtile_7__pin_inpad_0_),
.ccff_head(grid_io_right_0_ccff_tail),
.ccff_head(grid_clb_2_ccff_tail),
.chany_bottom_out(sb_2__2__0_chany_bottom_out[0:9]),
.chanx_left_out(sb_2__2__0_chanx_left_out[0:9]),
.ccff_tail(sb_2__2__0_ccff_tail));
@ -1074,7 +1074,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__0__0_chany_top_out[0:9]),
.chany_top_in(sb_0__1__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__0__0_ccff_tail),
.ccff_head(sb_0__1__0_ccff_tail),
.chany_bottom_out(cby_0__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_),
@ -1093,7 +1093,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_0__1__0_chany_top_out[0:9]),
.chany_top_in(sb_0__2__0_chany_bottom_out[0:9]),
.ccff_head(sb_0__1__0_ccff_tail),
.ccff_head(sb_0__2__0_ccff_tail),
.chany_bottom_out(cby_0__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_0__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_0__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_),
@ -1112,7 +1112,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__0__0_chany_top_out[0:9]),
.chany_top_in(sb_1__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__0_ccff_tail),
.ccff_head(cbx_1__1__0_ccff_tail),
.chany_bottom_out(cby_1__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__0_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_),
@ -1129,7 +1129,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_1__1__0_chany_top_out[0:9]),
.chany_top_in(sb_1__2__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__0_ccff_tail),
.ccff_head(cbx_1__2__0_ccff_tail),
.chany_bottom_out(cby_1__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_1__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_clk_0_(cby_1__1__1_right_grid_left_width_0_height_0_subtile_0__pin_clk_0_),
@ -1146,7 +1146,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_2__0__0_chany_top_out[0:9]),
.chany_top_in(sb_2__1__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__0__1_ccff_tail),
.ccff_head(cbx_1__1__1_ccff_tail),
.chany_bottom_out(cby_2__1__0_chany_bottom_out[0:9]),
.chany_top_out(cby_2__1__0_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__0_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),
@ -1170,7 +1170,7 @@ wire [0:9] sb_2__2__0_chany_bottom_out;
.prog_clk(prog_clk),
.chany_bottom_in(sb_2__1__0_chany_top_out[0:9]),
.chany_top_in(sb_2__2__0_chany_bottom_out[0:9]),
.ccff_head(cbx_1__1__1_ccff_tail),
.ccff_head(cbx_1__2__1_ccff_tail),
.chany_bottom_out(cby_2__1__1_chany_bottom_out[0:9]),
.chany_top_out(cby_2__1__1_chany_top_out[0:9]),
.right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_(cby_2__1__1_right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_),

72
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
View File

@ -1,56 +1,56 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="130" mux_size="4">
<driver_node type="CHANY" side="top" node_id="474" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="475" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="484" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="485" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="474" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="475" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="484" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="485" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="88" mux_size="4">
<driver_node type="CHANY" side="top" node_id="476" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="477" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="486" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="487" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="476" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="477" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="486" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="487" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="89" mux_size="4">
<driver_node type="CHANY" side="top" node_id="478" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="479" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="488" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="489" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="478" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="479" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="488" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="489" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="90" mux_size="4">
<driver_node type="CHANY" side="top" node_id="480" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="481" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="490" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="491" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="480" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="481" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="490" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="491" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="91" mux_size="4">
<driver_node type="CHANY" side="top" node_id="482" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="483" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="492" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="493" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="482" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="483" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="492" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="493" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="92" mux_size="4">
<driver_node type="CHANY" side="top" node_id="474" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="475" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="484" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="485" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="474" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="475" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="484" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="485" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="93" mux_size="4">
<driver_node type="CHANY" side="top" node_id="476" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="477" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="486" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="487" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="476" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="477" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="486" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="487" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="94" mux_size="4">
<driver_node type="CHANY" side="top" node_id="478" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="479" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="488" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="489" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="478" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="479" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="488" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="489" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="95" mux_size="4">
<driver_node type="CHANY" side="top" node_id="480" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="481" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="490" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="491" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="480" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="481" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="490" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="491" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,56 +1,56 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="264" mux_size="4">
<driver_node type="CHANY" side="top" node_id="494" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="477" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="482" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="487" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="494" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="477" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="482" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="487" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="222" mux_size="4">
<driver_node type="CHANY" side="top" node_id="474" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="479" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="484" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="489" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="474" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="479" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="484" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="489" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="223" mux_size="4">
<driver_node type="CHANY" side="top" node_id="476" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="481" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="486" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="497" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="476" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="481" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="486" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="497" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="224" mux_size="4">
<driver_node type="CHANY" side="top" node_id="478" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="495" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="498" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="493" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="478" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="495" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="498" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="493" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="225" mux_size="4">
<driver_node type="CHANY" side="top" node_id="496" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="485" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="490" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="499" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="496" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="485" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="490" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="499" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="226" mux_size="4">
<driver_node type="CHANY" side="top" node_id="494" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="477" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="482" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="487" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="494" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="477" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="482" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="487" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="227" mux_size="4">
<driver_node type="CHANY" side="top" node_id="474" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="479" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="484" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="489" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="474" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="479" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="484" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="489" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" node_id="228" mux_size="4">
<driver_node type="CHANY" side="top" node_id="476" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="481" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="486" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="497" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="476" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="481" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="486" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="497" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" node_id="229" mux_size="4">
<driver_node type="CHANY" side="top" node_id="478" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="495" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="498" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="493" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="478" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="495" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="498" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="493" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

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<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="165" mux_size="4">
<driver_node type="CHANY" side="top" node_id="500" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="501" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="510" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="511" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="500" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="501" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="510" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="511" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="118" mux_size="4">
<driver_node type="CHANY" side="top" node_id="502" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="503" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="512" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="513" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="502" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="503" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="512" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="513" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="119" mux_size="4">
<driver_node type="CHANY" side="top" node_id="504" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="505" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="514" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="515" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="504" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="505" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="514" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="515" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="120" mux_size="4">
<driver_node type="CHANY" side="top" node_id="506" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="507" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="516" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="517" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="506" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="507" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="516" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="517" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="121" mux_size="4">
<driver_node type="CHANY" side="top" node_id="508" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="509" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="518" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="519" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="508" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="509" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="518" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="519" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="122" mux_size="4">
<driver_node type="CHANY" side="top" node_id="500" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="501" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="510" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="511" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="500" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="501" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="510" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="511" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="123" mux_size="4">
<driver_node type="CHANY" side="top" node_id="502" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="503" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="512" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="513" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="502" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="503" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="512" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="513" index="13" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,44 +1,44 @@
<rr_cb x="1" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="299" mux_size="4">
<driver_node type="CHANY" side="top" node_id="520" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="503" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="508" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="513" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="520" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="503" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="508" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="513" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="252" mux_size="4">
<driver_node type="CHANY" side="top" node_id="500" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="505" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="510" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="515" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="500" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="505" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="510" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="515" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="253" mux_size="4">
<driver_node type="CHANY" side="top" node_id="502" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="507" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="512" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="523" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="502" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="507" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="512" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="523" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="254" mux_size="4">
<driver_node type="CHANY" side="top" node_id="504" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="521" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="524" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="519" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="504" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="521" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="524" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="519" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="255" mux_size="4">
<driver_node type="CHANY" side="top" node_id="522" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="511" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="516" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="525" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="522" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="511" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="516" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="525" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="256" mux_size="4">
<driver_node type="CHANY" side="top" node_id="520" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="503" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="508" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="513" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="520" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="503" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="508" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="513" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="257" mux_size="4">
<driver_node type="CHANY" side="top" node_id="500" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="505" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="510" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="515" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="500" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="505" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="510" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="515" index="13" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,86 +1,86 @@
<rr_cb x="2" y="1" num_sides="4">
<IPIN side="right" index="0" node_id="190" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="537" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="191" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="192" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="193" mux_size="4">
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="543" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="194" mux_size="4">
<driver_node type="CHANY" side="top" node_id="534" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="535" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="544" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="545" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="534" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="535" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="544" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="545" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="195" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="537" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="196" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="197" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="153" mux_size="4">
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="543" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="154" mux_size="4">
<driver_node type="CHANY" side="top" node_id="534" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="535" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="544" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="545" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="534" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="535" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="544" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="545" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="155" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="537" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="527" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="537" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="156" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="157" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="540" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="158" mux_size="4">
<driver_node type="CHANY" side="top" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="543" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="532" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="542" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="543" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

112
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View File

@ -1,86 +1,86 @@
<rr_cb x="2" y="2" num_sides="4">
<IPIN side="right" index="0" node_id="324" mux_size="4">
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" node_id="325" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" node_id="326" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="549" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" node_id="327" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="545" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" node_id="328" mux_size="4">
<driver_node type="CHANY" side="top" node_id="548" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="537" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="542" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="551" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="548" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="537" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="542" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="551" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" node_id="329" mux_size="4">
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" node_id="330" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" node_id="331" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="549" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" node_id="287" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="545" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" node_id="288" mux_size="4">
<driver_node type="CHANY" side="top" node_id="548" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="537" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="542" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="551" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="548" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="537" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="542" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="551" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" node_id="289" mux_size="4">
<driver_node type="CHANY" side="top" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="539" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="546" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="529" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="534" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="539" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" node_id="290" mux_size="4">
<driver_node type="CHANY" side="top" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="541" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="526" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="531" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="536" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="541" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" node_id="291" mux_size="4">
<driver_node type="CHANY" side="top" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="549" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="528" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="533" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="538" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="549" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" node_id="292" mux_size="4">
<driver_node type="CHANY" side="top" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" node_id="545" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="530" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="547" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="550" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" node_id="545" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,56 +1,56 @@
<rr_cb x="0" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,56 +1,56 @@
<rr_cb x="0" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,44 +1,44 @@
<rr_cb x="1" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,44 +1,44 @@
<rr_cb x="1" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
</rr_cb>

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@ -1,86 +1,86 @@
<rr_cb x="2" y="1" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
</rr_cb>

112
openfpga_flow/tasks/basic_tests/no_time_stamp/no_cout_in_gsb/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_2__2_.xml
View File

@ -1,86 +1,86 @@
<rr_cb x="2" y="2" num_sides="4">
<IPIN side="right" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="right" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="right" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="right" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="right" index="6" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="right" index="7" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="0" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
<IPIN side="left" index="1" mux_size="4">
<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="8" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="9" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="18" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="19" segment_id="0"/>
</IPIN>
<IPIN side="left" index="2" mux_size="4">
<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="0" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="1" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="10" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="11" segment_id="0"/>
</IPIN>
<IPIN side="left" index="3" mux_size="4">
<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="2" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="3" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="12" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="13" segment_id="0"/>
</IPIN>
<IPIN side="left" index="4" mux_size="4">
<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="4" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="5" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="14" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="15" segment_id="0"/>
</IPIN>
<IPIN side="left" index="5" mux_size="4">
<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="6" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="7" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="16" segment_id="0"/>
<driver_node type="CHANY" side="bottom" index="17" segment_id="0"/>
</IPIN>
</rr_cb>