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[core] typo

This commit is contained in:
tangxifan 2024-07-10 14:12:49 -07:00
parent af996e563e
commit 977283dd34
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
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@ -4,7 +4,7 @@
////////////////////////////////////////
`timescale 1ns / 1ps
module clk_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);
module rst_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);
input wire rst_cond_i;
input wire rst_i;

2
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_internal_driver/config/task.conf
View File

@ -32,7 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
[SYNTHESIS_PARAM]
# Yosys script parameters