[test] add a new test to validate reset generated by internal driver through programmable clock network
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tangxifan
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213914e4ac
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af996e563e
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@ -0,0 +1,26 @@
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/////////////////////////////////////////
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// Functionality: A locally generated reset signal which is to test clock network with internal drivers
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// Author: Xifan Tang
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////////////////////////////////////////
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`timescale 1ns / 1ps
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module clk_cond(rst_i, rst_cond_i, clk_i, d_i, q_o);
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input wire rst_cond_i;
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input wire rst_i;
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input wire clk_i;
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input wire d_i;
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output reg q_o;
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wire int_rst;
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assign int_rst = rst_cond_i & rst_i;
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always @(posedge int_rst or posedge clk_i) begin
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if (int_rst) begin
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q_o <= 0;
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end else begin
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q_o <= d_i;
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end
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end
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endmodule
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<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
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<clock_network name="clk_tree_2lvl" global_port="op_clk[0:0]">
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<spine name="clk_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="clk_rib_lvl1_sw0_upper" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw0_lower" x="1" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="clk_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="clk_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
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</taps>
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</clock_network>
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<clock_network name="rst_tree_2lvl" global_port="op_reset[0:0]">
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<spine name="rst_spine_lvl0" start_x="1" start_y="1" end_x="2" end_y="1">
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<switch_point tap="rst_rib_lvl1_sw0_upper" x="1" y="1">
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<internal_driver tile_pin="clb.O[0:7]"/>
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</switch_point>
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<switch_point tap="rst_rib_lvl1_sw0_lower" x="1" y="1">
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<internal_driver tile_pin="clb.O[0:7]"/>
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</switch_point>
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<switch_point tap="rst_rib_lvl1_sw1_upper" x="2" y="1"/>
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<switch_point tap="rst_rib_lvl1_sw1_lower" x="2" y="1"/>
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</spine>
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<spine name="rst_rib_lvl1_sw0_upper" start_x="1" start_y="2" end_x="1" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw0_lower" start_x="1" start_y="1" end_x="1" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
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<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
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<taps>
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<all from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]"/>
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</taps>
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</clock_network>
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</clock_networks>
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<pin_constraints>
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<!-- For a given .blif file, we want to assign
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- the reset signal to the op_reset[0] port of the FPGA fabric
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-->
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<set_io pin="op_reset[0]" net="int_rst"/>
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<set_io pin="op_clk[0]" net="clk_i"/>
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</pin_constraints>
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@ -32,6 +32,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/clk_cond/clk_cond.v
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/rst_cond/rst_cond.v
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[SYNTHESIS_PARAM]
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# Yosys script parameters
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@ -44,6 +45,12 @@ bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosy
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bench0_top = clk_cond
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bench0_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_clk_cond.xml
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bench0_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_clk_cond.xml
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bench0_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_clk.xml
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bench1_top = rst_cond
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bench1_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_cond.xml
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bench1_openfpga_vpr_constraint_file=${PATH:TASK_DIR}/config/vpr_constraint_rst_cond.xml
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bench1_openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_1rst_2layer_int_driver_rst.xml
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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@ -0,0 +1,12 @@
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<vpr_constraints tool_name="vpr">
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<partition_list>
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<partition name="q_o_part">
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<add_atom name_pattern="q_o"/>
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<add_region x_low="1" y_low="2" x_high="1" y_high="2"/>
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</partition>
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<partition name="int_rst_part">
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<add_atom name_pattern="int_rst*"/>
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<add_region x_low="1" y_low="1" x_high="1" y_high="1"/>
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</partition>
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</partition_list>
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</vpr_constraints>
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