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[test] typo

This commit is contained in:
tangxifan 2024-08-09 17:10:51 -07:00
parent a05bfb55dd
commit c6246ae905
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml
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@ -16,10 +16,10 @@
<spine name="rib_lvl1_sw2_lower" start_x="2" start_y="1" end_x="2" end_y="0" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_top[0:5].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_right[0:2].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_bottom[0:3].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_left[0:3].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_top[0:11].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_right[0:5].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_bottom[0:7].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_left[0:7].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>