205e9aa67b
[test] add a new test case
2023-05-26 20:55:52 -07:00
77be053966
[test] mock wrapper does not need bitstream forcing
2023-05-26 18:50:54 -07:00
7fbe567d4c
[test] add more testcases
2023-05-25 20:24:02 -07:00
812553e13d
[test] adding more test cases
2023-05-25 20:17:23 -07:00
11832ad22c
[test] add a new testcase to validate mock wrapper
2023-05-25 20:02:10 -07:00
7da7d03db5
[script] add example script for mock wrapper
2023-05-25 19:59:14 -07:00
f89b7a82cf
[arch] fixed a bug where the array size mismatch the layout name
2023-05-03 22:23:20 +08:00
8d02a6e600
[test] now testcases are using proper arch
2023-05-03 21:47:21 +08:00
df771cb33a
[test] add a new testcase for subtile and deploy it to basic regression test
2023-05-03 15:41:29 +08:00
a3f2ae3c33
[arch] format
2023-05-03 15:23:47 +08:00
02a5057449
[arch] add openfpga arch example using subtile; updated documentation
2023-05-03 15:20:49 +08:00
68f2d9fe5e
[arch] add new example arch using subtile in I/O blocks; Updated documentation
2023-05-03 15:16:39 +08:00
f06248a1b0
[test] add a new testcase to validate the ccff v2
2023-04-24 14:55:22 +08:00
02e964b16f
[test] add a new test case for ccffv2
2023-04-22 15:41:19 +08:00
087636cefa
[test] deploy new test to regression tests
2023-04-20 15:06:47 +08:00
40598d25a3
[core] fixed a bug which causes multi-clock programmable network failed in routing
2023-04-20 15:05:45 +08:00
fba0a83679
[test] debugging 2-clock network
2023-04-20 14:44:01 +08:00
02b02d18a5
[test] fixed a bug in clock arch
2023-04-20 11:35:36 +08:00
b242fd97d6
[test] adding new arch and testcase for 2-clock network
2023-04-20 11:31:49 +08:00
03cb664049
[test] now clock network example script supports multiple clocks
2023-04-20 10:56:36 +08:00
7d333b3669
[test] add a new test for clock network: validate full testbench is working
2023-04-20 10:36:08 +08:00
1f9c1fe7e1
[test] clean up clock network task config
2023-04-20 10:31:22 +08:00
571a012724
[test] xml format
2023-03-07 18:47:55 -08:00
7e3b656c51
[test] fixed a bug in arch
2023-03-06 23:06:32 -08:00
fd1c4039d3
[test] typo
2023-03-02 21:37:24 -08:00
02b50e3464
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
2023-03-02 21:33:32 -08:00
b9f7c72a96
[test] fixed some bugs in arch
2023-03-02 18:16:59 -08:00
5917446fbe
[arch] code format
2023-02-28 22:01:49 -08:00
780dec6b1b
[test] add a new test to validate the programmable clock arch
2023-02-28 21:46:57 -08:00
4f6b8c0905
Updated regression tests
2023-02-11 22:11:06 -07:00
f7c710e95e
renamed yosys_vpr_template fabric_netlist_gen_template
2023-02-11 18:33:06 -07:00
b2bdfb7475
Strip down task
2023-02-11 18:32:06 -07:00
b71a1014e8
renamed vpr_blif_template to fabric_verification_template
2023-02-11 18:29:21 -07:00
6a48f1eb05
Updated demo projects
2023-02-11 18:24:20 -07:00
a6263c44af
Updated format
2023-02-11 18:12:04 -07:00
2afb91596f
Refactored run_openfpga_task.py
2023-02-11 18:04:54 -07:00
57cec96d7e
[script] wrong path to yosys bin
2023-02-03 22:54:22 -08:00
ff31a7b828
[script] fixed the path to yosys bin for openfpga flow
2023-02-03 22:12:03 -08:00
aff8178581
[test] fixed remaining bugs
2023-01-24 18:00:04 -08:00
d1e951e52e
[test] debugging
2023-01-24 17:57:34 -08:00
f964c9ed67
[test] debug
2023-01-24 15:48:57 -08:00
8174f53796
[test] deploy new test to fpga bitstream regression
2023-01-24 15:42:01 -08:00
499d352cff
[flow] add yosys rewrite scripts
2023-01-24 15:39:42 -08:00
e7a3b48475
[arch] comment on the wrong mode bits
2023-01-24 15:24:17 -08:00
fec84d76d1
[arch] adding tech lib;
2023-01-24 15:22:34 -08:00
1d8c1a6803
[arch] adding a new arch to validate fracturable dsp
2023-01-24 15:17:50 -08:00
d60d0540da
[test] adding a new test case to validate the bitstream overloading for DSP blocks
2023-01-24 14:58:52 -08:00
f586229b97
[test] enable rst_on_lut benchmark
2023-01-18 19:45:41 -08:00
b7a66705e0
[test] now use yosys_vpr flow; add rst_on_lut benchmark
2023-01-18 19:42:50 -08:00
bc51be4863
[benchmark] syntax
2023-01-18 18:34:24 -08:00
e974e5ddf7
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
2023-01-18 18:31:36 -08:00
acc905fa11
[arch] add support to route reset to LUTs
2023-01-18 18:22:37 -08:00
95dd4fd535
[test] deploy new test to basic regression tests
2023-01-18 18:17:53 -08:00
03273371c0
[test] add a new test to validate local reset
2023-01-18 18:17:14 -08:00
c9e00b7abc
[arch] add a new example arch that supports local reset
2023-01-18 18:05:52 -08:00
b6ae829518
[benchmark] add a new benchmark to validate dff
2023-01-18 17:59:52 -08:00
2c9593c1d4
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
2023-01-15 13:09:40 -08:00
13aed6fff5
[test] still commment verification out
2023-01-15 12:17:59 -08:00
758cc7a089
[test] debugging
2023-01-15 11:44:48 -08:00
14bb76ec87
[test] remove verification steps for new test but leave a todo
2023-01-14 23:06:54 -08:00
297092f1fe
[arch] now use a local clock as an input of a CLB
2023-01-14 22:12:00 -08:00
5aa85d82e6
[test] deploy the new test to basic regression tests
2023-01-13 22:07:45 -08:00
9222d085cd
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
2023-01-13 22:04:56 -08:00
26f71656de
[test] update pin constraints
2023-01-13 21:12:18 -08:00
9e462d96e0
[arch] now use a dedicated input for locally generated clock signals
2023-01-13 20:46:04 -08:00
93107c752a
[test] updating test case
2023-01-13 19:53:15 -08:00
1fb39f803b
[doc] updated vpr arch naming rules
2023-01-13 19:52:58 -08:00
a06ee30ca0
[arch] added a new vpr arch where clock can be generated by internal logics
2023-01-13 19:35:00 -08:00
1353577351
[test] added a new test to validate locally generated clocks
2023-01-13 16:45:30 -08:00
6400605603
[benchmark] add clock divider
2023-01-13 16:39:06 -08:00
bbf83101be
[test] deploy new test to ci
2023-01-11 17:11:28 -08:00
c7dc3ce7dc
[test] pass
2023-01-11 17:10:29 -08:00
f6f153ace4
[test] debugging
2023-01-11 17:06:31 -08:00
d5ebbeea9a
[test] adding a new test to show how to automate generation of bus group files
2023-01-11 16:59:54 -08:00
54c3b965f2
[script] fixed a bug
2023-01-01 17:19:11 -08:00
3c8e157d7b
[script] rename and fix typo
2023-01-01 17:13:23 -08:00
43cb498827
[test] deploy new tests to basic regression tests
2023-01-01 17:07:25 -08:00
83d7ff56e1
[script] add dedicated testcase for source commands
2023-01-01 17:04:24 -08:00
cdec0cf28c
[script] add a custom variable to specify the path to openfpga shell script
2023-01-01 16:51:21 -08:00
c50daf273c
[script] add example script for using source command
2023-01-01 16:50:10 -08:00
d7a95a8ec2
[script] fixed some bugs
2022-12-30 18:30:52 -08:00
56a3e6e463
[test] reduce test size
2022-12-30 18:28:17 -08:00
93b020b0b3
[test] deploy new test to basic regression tests
2022-12-30 18:26:22 -08:00
ae11a4fbf2
[test] add a new test case
2022-12-30 18:25:15 -08:00
6973e9fb98
[script] add an example script for vpr standalone calls
2022-12-30 18:23:14 -08:00
c33b9f1b9b
[script] enable eval mode in tcl reg test
2022-12-02 12:07:27 -08:00
156fac9fec
[ci] deploy tcl test to ci
2022-12-02 11:46:14 -08:00
97c72c73f1
[test] add a small test to validate tcl integration
2022-12-02 11:43:46 -08:00
729a3a0249
[engine] tcl integration has initial success. Upload example scripts
2022-12-01 16:31:15 -08:00
9d8f4c1664
[script] format python codes
2022-11-21 14:21:31 -08:00
12d114bbae
[test] hit the bug of tileable rr_graph skip it
2022-11-05 10:52:04 -07:00
dc24e41c6b
[test] relax minW for counter128, as VPR's router degrades in routability
2022-11-03 19:48:13 -07:00
513f7800aa
[test] update golden outputs for no_cout_in_gsb testcase
2022-11-03 17:51:51 -07:00
a88bc2d4de
[test] update golden outputs for device4x4
2022-11-03 17:51:08 -07:00
5f74367c2e
[test] update golden for device1x1 no time stamp netlists
2022-11-03 17:48:40 -07:00
958ef37a83
Merge pull request #864 from yunuseryilmaz18/master
...
Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
2022-10-30 12:16:21 -07:00
1abd6bca42
Merge branch 'master' into master
2022-10-27 10:18:59 -07:00
67a77d863e
Update dpram.v
2022-10-27 08:29:56 +03:00
0fe3bd36b6
Update dpram16k.v
2022-10-27 08:28:58 +03:00
74568b13a2
Update dpram1k.v
2022-10-26 16:32:14 +03:00
64b5b5c31c
Update dpram_2048x8.v
2022-10-26 16:31:16 +03:00
f8b170ba75
Update dpram16k.v
2022-10-26 16:27:30 +03:00
82d8630ed4
Merge branch 'master' into patch-3
2022-10-24 13:32:42 +03:00
40f1f2fbc6
[test] update golden results for iwls
2022-10-21 20:28:10 -07:00
04286508c8
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
2022-10-21 20:26:56 -07:00
62a437a3a1
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
db0e5dff93
Added new cell library for fracturable dsp36
...
Added new divisible 36x36 multiplier cell library for architectures which has fracturable dsp36:
- The 36x36 multiplier is form from sixteen 9x9 multipliers.
- It operates same modes with existing library. It can operate in 3 fracturable modes:
1. one 36-bit multiplier
2. two 18-bit multipliers
3. four 9-bit multipliers
- It provides ~%20 better area than existing cell library (mult_36x36.v)
Comparison made with Synopsys Design Compiler NXT:
mult_36x36.v Total cell area 20470 um2
frac_mult_36x36.v Total cell area 15103 um2
2022-10-21 17:30:20 +03:00
29d4b3cced
Update frac_mem_32k.v
...
1. Mixed use of non-blocking and blocking statements are unsynthesizable in Synopsys Design Compiler.
2. While defining a multidimensional array, the first array size is for the length and the second one is for the depth. The order for ram_a and ram_b arrays was wrong and it caused "out of bounds" error in DC.
2022-10-20 09:48:29 +03:00
00a485cbeb
[test] add missing file
2022-10-17 19:44:25 -07:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
8b00bfdff9
[test] replace hardcoded paths in task config files with relative paths
2022-10-17 11:55:57 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
e9ee039e60
Merge branch 'master' into rst_on_lut_strong
2022-10-13 16:01:57 -07:00
33e2b16cb1
[arch] fixed a bug which caused verification failed
2022-10-13 15:33:43 -07:00
1c36ac28f1
[arch] code format
2022-10-13 12:17:32 -07:00
32f48f16c7
[arch] fixed a few bugs
2022-10-13 11:54:58 -07:00
b0be27b384
[test] add repack design constraints files
2022-10-13 11:22:48 -07:00
5cf315958d
[test] deploy new test to basic regression tests
2022-10-13 11:17:34 -07:00
7b7217d116
[arch]add new arch to test
2022-10-13 11:08:51 -07:00
7f67794787
[arch]add new arch to test
2022-10-13 10:54:40 -07:00
d7a253408d
Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 14:00:59 +03:00
6f55371d4b
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 13:53:32 +03:00
f62d435b1e
Update frac_mem_32k.v
2022-10-12 09:35:35 +03:00
35869b480a
Merge branch 'master' into xmllint
2022-10-07 10:47:43 -07:00
85089cbc88
[arch] apply xml format for all the architecture files
2022-10-07 10:31:51 -07:00
508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-07 09:38:07 +03:00
ab53f88c2b
[test] now use a fixed device layout for the single-mode LUT design testcase
2022-10-04 10:05:22 -07:00
13c819bb28
[ci] deply new test to ci
2022-10-01 11:04:08 -07:00
4eaecde0b9
[test] add golden netlists to ensure no cout in gsb
2022-10-01 11:03:13 -07:00
78f30cf072
[test] add a new test to track the golden netlists where cout is not in GSB
2022-09-30 15:38:27 -07:00
0d8d8446ee
[test] fixed a bug where OPIN for direct connection is included in GSB
2022-09-30 15:24:51 -07:00
088ff1a474
[script] fixed a bug
2022-09-29 16:27:03 -07:00
0565ca7aca
[script] add missing files
2022-09-29 16:14:38 -07:00
a3e7133d63
Merge branch 'master' into wire_lut_test
2022-09-29 16:02:18 -07:00
2ed4a60f36
[arch] reduce clb inputs to force net remapping during routing
2022-09-29 15:52:30 -07:00
ce0fbe1765
[test] fixed a few bugs
2022-09-29 15:32:31 -07:00
9bc9b61d35
[test] fixed a few bugs
2022-09-29 15:11:30 -07:00
f5e7ec4dd1
[test] add a new test case to validate wire lut case
2022-09-29 14:28:59 -07:00
df1ae7ba2a
[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
2022-09-29 14:23:17 -07:00
f7a02422b5
[arch] add a new arch to reproduce the wire-lut bug in repacker
2022-09-29 13:59:08 -07:00
3f8e2ade2e
[script] update missing scripts required by pb_pin_fixup test cases
2022-09-29 13:39:46 -07:00
49fa783914
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
2022-09-29 10:45:27 -07:00
79b260f5e1
[arch] update missing arch
2022-09-21 16:52:32 -07:00
b1f8cdab3c
[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
2022-09-21 15:28:56 -07:00
eaa0b5588a
[test] fixed a bug in pin constrain examples
2022-09-21 14:10:12 -07:00
b532bca9d2
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
2022-09-21 10:54:16 -07:00
baac236ed7
[test] fixed a bug in example scripts due to the changes on vpr options
2022-09-21 10:52:49 -07:00
d0b018ad6e
[script] mismatches in vpr options due to upgrade
2022-09-21 09:27:26 -07:00
40edf859e3
Merge branch 'vtr_upgrade' of github.com:lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-20 22:38:06 -07:00
97f0445787
[arch] upgrade arch file which was designed for v1.1
2022-09-20 22:37:35 -07:00
tangxifan
Ganesh Gore
Yunus Emre ERYILMAZ
mustafa.arslan