[test] fixed remaining bugs

openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow_with_rewrite.ys

@@ -1,7 +1,7 @@
 # Yosys synthesis script for ${TOP_MODULE}
 # Read verilog files
 read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES}
-read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
+read_verilog ${READ_VERILOG_OPTIONS} ${YOSYS_CELL_SIM_VERILOG}
 
 # Technology mapping
 hierarchy -top ${TOP_MODULE}