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[test] mock wrapper does not need bitstream forcing

This commit is contained in:
tangxifan 2023-05-26 18:50:54 -07:00
parent a9e5e1af89
commit 77be053966
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/mock_wrapper_example_script.openfpga
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@ -52,7 +52,7 @@ write_mock_fpga_wrapper --file ./SRC ${OPENFPGA_MOCK_WRAPPER_OPTIONS} ${OPENFPGA
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_preconfigured_fabric_wrapper --embed_bitstream none --file ./SRC --explicit_port_mapping
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
# Write the SDC files for PnR backend