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[arch] now use a local clock as an input of a CLB

This commit is contained in:
tangxifan 2023-01-14 22:12:00 -08:00
parent 5aa85d82e6
commit 297092f1fe
2 changed files with 10 additions and 6 deletions
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4
openfpga_flow/openfpga_arch/k4_frac_N4_fracff_localClkGen_40nm_cc_openfpga.xml
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@ -200,8 +200,8 @@
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<tile_annotations>
<global_port name="op_clk" tile_port="clb.clk[1]" is_clock="true" default_val="0">
<tile name="clb" port="clk[1]"/>
<global_port name="op_clk" tile_port="clb.clk" is_clock="true" default_val="0">
<tile name="clb" port="clk"/>
</global_port>
<global_port name="op_reset" is_reset="true" default_val="0">
<tile name="clb" port="reset"/>

12
openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_localClkGen_40nm.xml
View File

@ -102,9 +102,11 @@
<input name="I" num_pins="12" equivalent="full"/>
<input name="reset" num_pins="1" is_non_clock_global="true"/>
<output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="2" equivalent="full"/>
<!-- Local clock -->
<input name="lclk" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
<fc_override port_name="clk[1]" fc_type="frac" fc_val="0"/>
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
</fc>
<pinlocations pattern="spread"/>
@ -276,7 +278,9 @@
<input name="I" num_pins="12" equivalent="full"/>
<input name="reset" num_pins="1"/>
<output name="O" num_pins="8" equivalent="none"/>
<clock name="clk" num_pins="2" equivalent="full"/>
<!-- Local clock -->
<input name="lclk" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
The outputs of the fracturable logic element can be optionally registered
@ -611,7 +615,7 @@
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
</complete>
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
<complete name="clks" input="clb.lclk clb.clk" output="fle[3:0].clk">
</complete>
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
</complete>