Updated format
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@ -395,7 +395,7 @@ def main():
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def check_required_file():
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""" Function ensure existace of all required files for the script """
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"""Function ensure existace of all required files for the script"""
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files_dict = {
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"CAD TOOL PATH": os.path.join(
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flow_script_dir, os.pardir, "misc", "fpgaflow_default_tool_path.conf"
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@ -407,7 +407,7 @@ def check_required_file():
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def read_script_config():
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""" This fucntion reads default CAD tools path from configuration file """
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"""This fucntion reads default CAD tools path from configuration file"""
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global config, cad_tools
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config = ConfigParser(interpolation=ExtendedInterpolation())
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config.read_dict(script_env_vars)
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@ -72,9 +72,7 @@ parser.add_argument(
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help="Dummy run shows final generated VPR commands",
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)
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parser.add_argument("--debug", action="store_true", help="Run script in debug mode")
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parser.add_argument(
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"--continue_on_fail", action="store_true", help="Exit script with return code"
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)
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parser.add_argument("--continue_on_fail", action="store_true", help="Exit script with return code")
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parser.add_argument(
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"--show_thread_logs", action="store_true", help="Skips logs from running thread"
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)
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@ -87,24 +85,16 @@ task_script_dir = os.path.dirname(os.path.abspath(__file__))
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script_env_vars = {
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"PATH": {
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"OPENFPGA_FLOW_PATH": task_script_dir,
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"VPR_ARCH_PATH": os.path.join(
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"${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch"
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),
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"OF_ARCH_PATH": os.path.join(
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"${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch"
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),
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"VPR_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "vpr_arch"),
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"OF_ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "openfpga_arch"),
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"OPENFPGA_SHELLSCRIPT_PATH": os.path.join(
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"${PATH:OPENFPGA_PATH}", "openfpga_flow", "OpenFPGAShellScripts"
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),
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"BENCH_PATH": os.path.join(
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"${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks"
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),
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"BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "benchmarks"),
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"TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "openfpga_flow", "tech"),
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"SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
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"VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
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"OPENFPGA_PATH": os.path.abspath(
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os.path.join(task_script_dir, os.pardir, os.pardir)
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),
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"OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir, os.pardir)),
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}
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}
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config = ConfigParser(interpolation=ExtendedInterpolation())
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@ -252,8 +242,7 @@ def generate_each_task_actions(taskname):
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missing_section = list(set(required_sec) - set(task_conf.sections()))
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if missing_section:
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clean_up_and_exit(
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"Missing sections %s" % " ".join(missing_section)
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+ " in task configuration file"
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"Missing sections %s" % " ".join(missing_section) + " in task configuration file"
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)
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# Declare varibles to access sections
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@ -274,9 +263,7 @@ def generate_each_task_actions(taskname):
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clean_up_and_exit("Found duplicate architectures in config file")
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# Get Flow information
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logger.info(
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'Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr")
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)
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logger.info('Running "%s" flow', GeneralSection.get("fpga_flow", fallback="yosys_vpr"))
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# Check if specified benchmark files exist
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benchmark_list = []
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@ -290,8 +277,7 @@ def generate_each_task_actions(taskname):
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files = glob.glob(eachpath)
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if not len(files):
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clean_up_and_exit(
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("No files added benchmark %s" % bech_name)
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+ " with path %s " % (eachpath)
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("No files added benchmark %s" % bech_name) + " with path %s " % (eachpath)
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)
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bench_files += files
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@ -327,15 +313,11 @@ def generate_each_task_actions(taskname):
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yosys_params_common = {}
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for param in yosys_params:
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yosys_params_common[param.upper()] = SynthSection.get(
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"bench_" + param + "_common"
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)
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yosys_params_common[param.upper()] = SynthSection.get("bench_" + param + "_common")
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# Individual benchmark configuration
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CurrBenchPara["files"] = bench_files
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CurrBenchPara["top_module"] = SynthSection.get(
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bech_name + "_top", fallback="top"
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)
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CurrBenchPara["top_module"] = SynthSection.get(bech_name + "_top", fallback="top")
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CurrBenchPara["ys_script"] = SynthSection.get(
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bech_name + "_yosys", fallback=ys_for_task_common
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)
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@ -360,8 +342,7 @@ def generate_each_task_actions(taskname):
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if GeneralSection.getboolean("power_analysis"):
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if not SynthSection.get(bech_name + "_act"):
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clean_up_and_exit(
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"Missing argument %s" % (bech_name + "_act")
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+ "for vpr_blif flow"
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"Missing argument %s" % (bech_name + "_act") + "for vpr_blif flow"
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)
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CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act")
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else:
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@ -369,9 +350,7 @@ def generate_each_task_actions(taskname):
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if not SynthSection.get(bech_name + "_act"):
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CurrBenchPara["activity_file"] = bech_name + "_act"
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else:
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CurrBenchPara["activity_file"] = SynthSection.get(
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bech_name + "_act"
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)
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CurrBenchPara["activity_file"] = SynthSection.get(bech_name + "_act")
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# Check if base verilog file exists
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if not SynthSection.get(bech_name + "_verilog"):
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@ -413,10 +392,7 @@ def generate_each_task_actions(taskname):
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if benchmark_top_module_count.count(bench["top_module"]) > 1:
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flow_run_dir = get_flow_rundir(
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arch,
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"bench"
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+ str(benchmark_list.index(bench))
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+ "_"
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+ bench["top_module"],
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"bench" + str(benchmark_list.index(bench)) + "_" + bench["top_module"],
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lbl,
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)
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else:
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@ -593,11 +569,7 @@ def run_single_script(s, eachJob, job_list):
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os._exit(1)
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eachJob["endtime"] = time.time()
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timediff = timedelta(seconds=(eachJob["endtime"] - eachJob["starttime"]))
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timestr = (
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humanize.naturaldelta(timediff)
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if "humanize" in sys.modules
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else str(timediff)
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)
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timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules else str(timediff)
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logger.info(
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"%s Finished with returncode %d, Time Taken %s ",
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thread_name,
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@ -639,9 +611,7 @@ def collect_results(job_run_list):
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continue
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# Read and merge result file
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vpr_res = ConfigParser(
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allow_no_value=True, interpolation=ExtendedInterpolation()
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)
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vpr_res = ConfigParser(allow_no_value=True, interpolation=ExtendedInterpolation())
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vpr_result_file = os.path.join(run["run_dir"], "vpr_stat.result")
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vpr_res.read_file(open(vpr_result_file, encoding="UTF-8"))
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result = OrderedDict()
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