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[core] fixed a bug which causes multi-clock programmable network failed in routing

This commit is contained in:
tangxifan 2023-04-20 15:05:45 +08:00
parent fba0a83679
commit 40598d25a3
2 changed files with 15 additions and 10 deletions
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21
openfpga/src/annotation/route_clock_rr_graph.cpp
View File

@ -141,10 +141,13 @@ static int route_clock_tree_rr_graph(
VTR_ASSERT(rr_graph.valid_node(des_node));
vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node,
src_node);
vpr_routing_annotation.set_rr_node_net(src_node,
tree2clk_pin_map.at(ipin));
vpr_routing_annotation.set_rr_node_net(des_node,
tree2clk_pin_map.at(ipin));
/* It could happen that there is no net mapped some clock pin, skip the net mapping */
if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) {
vpr_routing_annotation.set_rr_node_net(src_node,
tree2clk_pin_map.at(ipin));
vpr_routing_annotation.set_rr_node_net(des_node,
tree2clk_pin_map.at(ipin));
}
}
/* Route the spine-to-IPIN connections (only for the last level) */
if (clk_ntwk.is_last_level(ispine)) {
@ -165,10 +168,12 @@ static int route_clock_tree_rr_graph(
VTR_ASSERT(rr_graph.valid_node(des_node));
vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node,
src_node);
vpr_routing_annotation.set_rr_node_net(src_node,
tree2clk_pin_map.at(ipin));
vpr_routing_annotation.set_rr_node_net(des_node,
tree2clk_pin_map.at(ipin));
if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) {
vpr_routing_annotation.set_rr_node_net(src_node,
tree2clk_pin_map.at(ipin));
vpr_routing_annotation.set_rr_node_net(des_node,
tree2clk_pin_map.at(ipin));
}
}
}
}

4
openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga
View File

@ -64,8 +64,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE}
# Finish and exit OpenFPGA