From 40598d25a3c08b5764f672c040d4b0030ca62982 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 20 Apr 2023 15:05:45 +0800 Subject: [PATCH] [core] fixed a bug which causes multi-clock programmable network failed in routing --- .../src/annotation/route_clock_rr_graph.cpp | 21 ++++++++++++------- .../example_clkntwk_script.openfpga | 4 ++-- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 2d4d152f6..03d083172 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -141,10 +141,13 @@ static int route_clock_tree_rr_graph( VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); - vpr_routing_annotation.set_rr_node_net(src_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); + /* It could happen that there is no net mapped some clock pin, skip the net mapping */ + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + } } /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { @@ -165,10 +168,12 @@ static int route_clock_tree_rr_graph( VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); - vpr_routing_annotation.set_rr_node_net(src_node, - tree2clk_pin_map.at(ipin)); - vpr_routing_annotation.set_rr_node_net(des_node, - tree2clk_pin_map.at(ipin)); + if (tree2clk_pin_map.find(ipin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(ipin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(ipin)); + } } } } diff --git a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga index cc74022f6..83cc44860 100644 --- a/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/example_clkntwk_script.openfpga @@ -64,8 +64,8 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit -write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --pin_constraints_file ${OPENFPGA_PIN_CONSTRAINTS_FILE} # Finish and exit OpenFPGA