00f39d55ab
[test] now use fixed routing channel width
2024-05-06 23:32:27 -07:00
3615bdceeb
[test] avoid no-fanin errors for hetero arch
2024-05-06 15:32:27 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
c334a0a792
[test] fixed a bug and add golden outputs
2024-05-02 22:07:22 -07:00
98006608c2
[test] add fabric hierarchy file to golden outputs
2024-05-02 22:03:23 -07:00
4e3bbbe45e
[test] add options to write fabric hierarchy file
2024-05-02 22:00:47 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
1af8a4ae4f
[test] add golden outputs
2024-04-11 15:20:34 -07:00
9b0a491819
[test] now validate no time stamp file for fabric pin physical location
2024-04-11 15:16:34 -07:00
d51832a4e2
[ci] typo
2024-04-11 15:13:20 -07:00
e85df6dcfd
[ci] deploy new tests to basic reg tests
2024-04-11 15:11:41 -07:00
20ba0e1dd5
[test] add new testcases to validate options of write_fabric_pin_physical_location
2024-04-11 15:06:50 -07:00
0c680ec426
[test] now test regex as module name for fabric pin physical location
2024-04-11 15:01:19 -07:00
4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
c63cee458b
[script] adapt code format for python
2024-04-10 12:58:05 -07:00
3824b006cc
[test] add new golden outputs
2024-03-29 12:06:00 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
20386945bd
[test] add a new testcase to validate dump waveform
2024-03-29 11:53:55 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
2bd60dad11
[script] now timing extraction focus on the last found results
2023-12-12 14:10:13 -08:00
592e2e310c
[script] typo
2023-12-12 13:45:23 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
c5cc05a9f5
[script] add a new example default tool path config with a focus on timing
2023-12-12 13:22:50 -08:00
f689ef7654
[script] format
2023-12-12 13:15:03 -08:00
4c0f6e2273
[script] syntax
2023-12-12 13:14:47 -08:00
e753e6d22c
[script] syntax
2023-12-12 13:13:51 -08:00
d9db78ac30
[script] now run fpga task has a new option ``default_tool_path``
2023-12-12 13:11:48 -08:00
1a4aaaf759
[script] update openfpga flow to support args for default tool path
2023-12-12 10:00:50 -08:00
a7b22163a8
[script] fixe the mismatch on keywords against latest vpr
2023-12-12 09:52:42 -08:00
5c839c1858
[test] debug
2023-12-08 13:52:52 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
99f1c5493c
[test] add a new testcase to support vcs
2023-12-08 13:45:23 -08:00
a1169beaf0
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:34:49 -08:00
7475a002b6
Update repack_design_constraints.xml by changing the separater between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:33:55 -08:00
6055a42196
add test case
2023-12-01 03:04:32 -08:00
dff03e7993
[test] enable missing options in the arch used by benchmark sweeping tests
2023-11-14 09:45:02 -08:00
0b473e3454
[test] fixed the bug in single-mode lut testcase
2023-11-14 09:35:26 -08:00
d108284105
[test] update arch to keep golden outputs
2023-11-14 09:31:07 -08:00
913434b70d
[test] fixed the bug that golden netlists are modified
2023-11-14 09:28:57 -08:00
59d086a27f
[test] try to keep the golden inputs
2023-11-14 09:25:45 -08:00
1b8748abb4
[core] update vtr
2023-11-13 14:21:34 -08:00
d78f18d235
[test] add new testcase
2023-11-13 14:11:34 -08:00
8e875f3453
[test] add a new test case to validate the new feature
2023-11-02 21:08:36 -07:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
60b8c396dc
[test] add a new test
2023-09-25 21:25:21 -07:00
a4f53c64c6
[test] fixed a bug
2023-09-25 19:28:19 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
a1ed277a88
[test] typo
2023-09-23 15:12:02 -07:00
00e1a5df11
[test] fixed some bugs
2023-09-23 12:44:47 -07:00
195aa7a9a8
[test] developing new test to increase coverage on module renaming
2023-09-23 12:40:20 -07:00
f3279bd885
[test] now use 4x4 fabric to check the using index netlists
2023-09-20 22:49:47 -07:00
eeb1bd6662
[core] fixed some bugs
2023-09-17 23:16:15 -07:00
3fd60a165d
[test] typo
2023-09-17 17:42:15 -07:00
11e976ec92
[test] add a new test to validate renaming on fpga top/core modules
2023-09-17 17:38:37 -07:00
0ef1e0bde5
[test] add a new test to validate renaming rules
2023-09-17 13:29:12 -07:00
559fa45d89
[test] add a new test to validate module renaming using index
2023-09-16 17:55:52 -07:00
1287097ce5
[test] update golden netlists
2023-09-06 22:51:38 -07:00
401f8098a6
[test] update golden copies
2023-09-06 17:35:03 -07:00
db0bb291c2
[test] update settings
2023-08-22 15:22:48 -07:00
56cedf6c8b
[test] added a new test case to validate the support on different wire segment distribution on X and Y
2023-08-22 11:20:14 -07:00
1b132fd667
[test] add a new testcase to validate the support on different routing channel width on X and Y
2023-08-22 11:06:12 -07:00
15a8d8a76a
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
2023-08-18 21:59:06 -07:00
5f6050d404
[test] add a new test to validate combo: group tile, tile annotation and subtile
2023-08-18 21:48:40 -07:00
e4c5265b68
[test] arch syntax
2023-08-18 21:40:56 -07:00
5ac8919ce0
[test] add a new testcase to validate subtile with tile annotations
2023-08-18 21:37:15 -07:00
f69520d0c3
[arch] format
2023-08-18 11:15:25 -07:00
170a49c34f
[test] fix a bug in arch file
2023-08-18 11:15:05 -07:00
e82e4f487e
[test] add a new test to validate io subtile support
2023-08-18 11:13:34 -07:00
4afd48d930
[test] format
2023-08-17 15:33:09 -07:00
463897f78e
[test] fixed a bug in arch
2023-08-17 15:28:59 -07:00
3ac3eb4624
[test] adding more flavor to the L shape
2023-08-17 15:08:27 -07:00
913c232556
[test] deploy new test to basic reg test
2023-08-17 14:54:24 -07:00
85bc890009
[test] add a new test to validate comb options of group tile, group config block and L shape fabric
2023-08-17 14:52:30 -07:00
2f49c25f09
[test] updated
2023-08-11 21:19:06 -07:00
b155e660ee
[test] fixed a bug
2023-08-11 16:55:35 -07:00
16f102f4c1
[test] deploy new tests to basic regression tests
2023-08-11 13:07:41 -07:00
253d5fa26c
[core] a new test to validate the L shape in homo geneous fpga
2023-08-11 13:05:46 -07:00
dc0eec8b81
[test] added a new test to validate L shapre
2023-08-11 12:49:38 -07:00
0e9cf6e909
[test] added a new testcase to validate heterogeneous fpga using group config block
2023-08-06 22:11:38 -07:00
3e33f262bc
[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
2023-08-06 18:59:24 -07:00
46b1de08c6
[test] fixed a bug
2023-08-05 22:07:46 -07:00
b7048d3dc8
[test] adding new tests to validate group config block
2023-08-03 22:30:41 -07:00
667c5f8944
[test] fixed a bug on the testcase
2023-07-27 22:02:28 -07:00
952e84fce1
[test] now heterogeneous testcases for tile modules pass
2023-07-27 20:30:32 -07:00
beaa687a20
[core] fixed bugs on supporting heterogeneous blocks in tile modules
2023-07-27 20:29:18 -07:00
3d56bd0ff2
[test] deploy the new test to ci
2023-07-27 17:03:55 -07:00
65995d7c13
[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
2023-07-27 17:03:02 -07:00
46e58a56cb
[test] added a new test case to validate clock network when using the tile modules
2023-07-27 16:39:48 -07:00
81d699a723
[test] added a new testcase to validate carry chain connections in tile modules
2023-07-27 16:18:30 -07:00
e9f2adf3f9
[test] add a new testcase to validate carry chain connections when using tile modules
2023-07-27 16:06:43 -07:00
1ea8a33d4b
[test] add a new testcase to validate global tile connections on tile modules
2023-07-27 15:57:38 -07:00
a2848940df
[test] add a new testcase to ease debugging
2023-07-26 22:32:03 -07:00
5685fbd5e8
[test] adding a new test case to validate the tile modules on 4x4 fabric
2023-07-26 22:17:39 -07:00
bb837f4f79
[test] update golden netlists
2023-07-25 23:39:59 -07:00
0db4ef62e8
[test] add a new test for tile-based fabric: using preconfig testbenches
2023-07-25 15:48:14 -07:00
523cf83cc9
[test] disable pnr writer in test cases
2023-07-25 15:39:25 -07:00
82fe63297a
[test] add a new test for top-left tile grouping
2023-07-19 11:22:36 -07:00
930d98f2af
[test] deploy new tests
2023-07-08 21:52:16 -07:00
124514c80e
[test] update fabric key to new syntax
2023-07-08 18:26:05 -07:00
51e1547634
[test] hotfix
2023-06-26 15:32:16 -07:00
270d6f933b
[test] add a new testcase to validate mock wrapper
2023-06-26 15:26:50 -07:00
919d6d8608
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
2023-06-25 22:49:51 -07:00
523e338d53
[test] debugging
2023-06-23 14:49:52 -07:00
962ba67e36
[test] adding new tests to validate fpga core wrapper naming rules
2023-06-23 14:47:21 -07:00
84edd41342
[test] fixed the bug in adder mapping
2023-06-20 17:09:31 -07:00
dba48fb171
[test] reworking adder mapping flow to validate carry chain mapping
2023-06-20 16:57:08 -07:00
fd8f371d85
[test] add missing file
2023-06-19 16:44:11 -07:00
efc9bf9907
[test] added new test case to validate bitstream generation
2023-06-19 12:40:37 -07:00
97b089ae3c
[test] added new testcases to validate fpga core wrapper
2023-06-18 21:01:37 -07:00
1ef8eed589
[test] update no time stamp golden outputs
2023-06-08 15:38:15 -07:00
ac31a20376
[test] now bypass clock routing in default example
2023-06-08 13:44:22 -07:00
31b16ba9d7
[test] fixed a few bugs
2023-05-27 12:47:57 -07:00
27b8007d1b
[test] rework pcf support testcase for mock wrapper
2023-05-27 12:45:29 -07:00
b3471f2703
[test] swap test name
2023-05-27 12:34:10 -07:00
89f184e779
[test] fixed a few bugs
2023-05-27 12:19:28 -07:00
b6c90eb99a
[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed
2023-05-27 12:13:16 -07:00
e1feebc96d
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
2023-05-26 21:54:08 -07:00
205e9aa67b
[test] add a new test case
2023-05-26 20:55:52 -07:00
77be053966
[test] mock wrapper does not need bitstream forcing
2023-05-26 18:50:54 -07:00
7fbe567d4c
[test] add more testcases
2023-05-25 20:24:02 -07:00
812553e13d
[test] adding more test cases
2023-05-25 20:17:23 -07:00
11832ad22c
[test] add a new testcase to validate mock wrapper
2023-05-25 20:02:10 -07:00
7da7d03db5
[script] add example script for mock wrapper
2023-05-25 19:59:14 -07:00
f89b7a82cf
[arch] fixed a bug where the array size mismatch the layout name
2023-05-03 22:23:20 +08:00
8d02a6e600
[test] now testcases are using proper arch
2023-05-03 21:47:21 +08:00
df771cb33a
[test] add a new testcase for subtile and deploy it to basic regression test
2023-05-03 15:41:29 +08:00
a3f2ae3c33
[arch] format
2023-05-03 15:23:47 +08:00
02a5057449
[arch] add openfpga arch example using subtile; updated documentation
2023-05-03 15:20:49 +08:00
68f2d9fe5e
[arch] add new example arch using subtile in I/O blocks; Updated documentation
2023-05-03 15:16:39 +08:00
f06248a1b0
[test] add a new testcase to validate the ccff v2
2023-04-24 14:55:22 +08:00
02e964b16f
[test] add a new test case for ccffv2
2023-04-22 15:41:19 +08:00
087636cefa
[test] deploy new test to regression tests
2023-04-20 15:06:47 +08:00
40598d25a3
[core] fixed a bug which causes multi-clock programmable network failed in routing
2023-04-20 15:05:45 +08:00
fba0a83679
[test] debugging 2-clock network
2023-04-20 14:44:01 +08:00
02b02d18a5
[test] fixed a bug in clock arch
2023-04-20 11:35:36 +08:00
b242fd97d6
[test] adding new arch and testcase for 2-clock network
2023-04-20 11:31:49 +08:00
03cb664049
[test] now clock network example script supports multiple clocks
2023-04-20 10:56:36 +08:00
7d333b3669
[test] add a new test for clock network: validate full testbench is working
2023-04-20 10:36:08 +08:00
1f9c1fe7e1
[test] clean up clock network task config
2023-04-20 10:31:22 +08:00
571a012724
[test] xml format
2023-03-07 18:47:55 -08:00
7e3b656c51
[test] fixed a bug in arch
2023-03-06 23:06:32 -08:00
fd1c4039d3
[test] typo
2023-03-02 21:37:24 -08:00
02b50e3464
[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
2023-03-02 21:33:32 -08:00
b9f7c72a96
[test] fixed some bugs in arch
2023-03-02 18:16:59 -08:00
5917446fbe
[arch] code format
2023-02-28 22:01:49 -08:00
780dec6b1b
[test] add a new test to validate the programmable clock arch
2023-02-28 21:46:57 -08:00
4f6b8c0905
Updated regression tests
2023-02-11 22:11:06 -07:00
f7c710e95e
renamed yosys_vpr_template fabric_netlist_gen_template
2023-02-11 18:33:06 -07:00
b2bdfb7475
Strip down task
2023-02-11 18:32:06 -07:00
b71a1014e8
renamed vpr_blif_template to fabric_verification_template
2023-02-11 18:29:21 -07:00
6a48f1eb05
Updated demo projects
2023-02-11 18:24:20 -07:00
a6263c44af
Updated format
2023-02-11 18:12:04 -07:00
2afb91596f
Refactored run_openfpga_task.py
2023-02-11 18:04:54 -07:00
57cec96d7e
[script] wrong path to yosys bin
2023-02-03 22:54:22 -08:00
ff31a7b828
[script] fixed the path to yosys bin for openfpga flow
2023-02-03 22:12:03 -08:00
aff8178581
[test] fixed remaining bugs
2023-01-24 18:00:04 -08:00
d1e951e52e
[test] debugging
2023-01-24 17:57:34 -08:00
f964c9ed67
[test] debug
2023-01-24 15:48:57 -08:00
8174f53796
[test] deploy new test to fpga bitstream regression
2023-01-24 15:42:01 -08:00
499d352cff
[flow] add yosys rewrite scripts
2023-01-24 15:39:42 -08:00
e7a3b48475
[arch] comment on the wrong mode bits
2023-01-24 15:24:17 -08:00
fec84d76d1
[arch] adding tech lib;
2023-01-24 15:22:34 -08:00
1d8c1a6803
[arch] adding a new arch to validate fracturable dsp
2023-01-24 15:17:50 -08:00
d60d0540da
[test] adding a new test case to validate the bitstream overloading for DSP blocks
2023-01-24 14:58:52 -08:00
f586229b97
[test] enable rst_on_lut benchmark
2023-01-18 19:45:41 -08:00
b7a66705e0
[test] now use yosys_vpr flow; add rst_on_lut benchmark
2023-01-18 19:42:50 -08:00
bc51be4863
[benchmark] syntax
2023-01-18 18:34:24 -08:00
e974e5ddf7
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
2023-01-18 18:31:36 -08:00
acc905fa11
[arch] add support to route reset to LUTs
2023-01-18 18:22:37 -08:00
95dd4fd535
[test] deploy new test to basic regression tests
2023-01-18 18:17:53 -08:00
03273371c0
[test] add a new test to validate local reset
2023-01-18 18:17:14 -08:00
c9e00b7abc
[arch] add a new example arch that supports local reset
2023-01-18 18:05:52 -08:00
b6ae829518
[benchmark] add a new benchmark to validate dff
2023-01-18 17:59:52 -08:00
2c9593c1d4
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
2023-01-15 13:09:40 -08:00
13aed6fff5
[test] still commment verification out
2023-01-15 12:17:59 -08:00
758cc7a089
[test] debugging
2023-01-15 11:44:48 -08:00
14bb76ec87
[test] remove verification steps for new test but leave a todo
2023-01-14 23:06:54 -08:00
297092f1fe
[arch] now use a local clock as an input of a CLB
2023-01-14 22:12:00 -08:00
5aa85d82e6
[test] deploy the new test to basic regression tests
2023-01-13 22:07:45 -08:00
9222d085cd
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
2023-01-13 22:04:56 -08:00
26f71656de
[test] update pin constraints
2023-01-13 21:12:18 -08:00
9e462d96e0
[arch] now use a dedicated input for locally generated clock signals
2023-01-13 20:46:04 -08:00
93107c752a
[test] updating test case
2023-01-13 19:53:15 -08:00
1fb39f803b
[doc] updated vpr arch naming rules
2023-01-13 19:52:58 -08:00
a06ee30ca0
[arch] added a new vpr arch where clock can be generated by internal logics
2023-01-13 19:35:00 -08:00
1353577351
[test] added a new test to validate locally generated clocks
2023-01-13 16:45:30 -08:00
6400605603
[benchmark] add clock divider
2023-01-13 16:39:06 -08:00
bbf83101be
[test] deploy new test to ci
2023-01-11 17:11:28 -08:00
c7dc3ce7dc
[test] pass
2023-01-11 17:10:29 -08:00
f6f153ace4
[test] debugging
2023-01-11 17:06:31 -08:00
d5ebbeea9a
[test] adding a new test to show how to automate generation of bus group files
2023-01-11 16:59:54 -08:00
54c3b965f2
[script] fixed a bug
2023-01-01 17:19:11 -08:00
3c8e157d7b
[script] rename and fix typo
2023-01-01 17:13:23 -08:00
43cb498827
[test] deploy new tests to basic regression tests
2023-01-01 17:07:25 -08:00
83d7ff56e1
[script] add dedicated testcase for source commands
2023-01-01 17:04:24 -08:00
cdec0cf28c
[script] add a custom variable to specify the path to openfpga shell script
2023-01-01 16:51:21 -08:00
c50daf273c
[script] add example script for using source command
2023-01-01 16:50:10 -08:00
d7a95a8ec2
[script] fixed some bugs
2022-12-30 18:30:52 -08:00
tangxifan
chungshien
Yitian4Debug
ubuntu
Ganesh Gore