a46820b7c1
[core] add a new test for bottom-left tile grouping
2024-07-05 18:00:37 -07:00
fe73e03c69
[test] changing arch
2024-07-04 21:31:43 -07:00
4064c29d49
[test] updating arch for perimeter cb
2024-07-04 21:23:15 -07:00
5865aebf93
[test] add new arch
2024-07-04 21:12:26 -07:00
a78fddc3cb
[test] add a new testcase to validate perimeter cb
2024-07-03 19:59:24 -07:00
078fad1e74
[test] typo
2024-07-02 14:57:24 -07:00
7e461b09f8
[core] add missing file
2024-07-02 13:22:41 -07:00
1e7cca8ceb
[arch] code format
2024-07-02 11:52:30 -07:00
29452a7442
[test] fixed a bug on out-of-date arch
2024-07-02 11:52:19 -07:00
9b5df76fd5
[test] fix a bug in arch
2024-07-02 09:33:16 -07:00
e00312d29e
[test] typo
2024-07-01 20:34:37 -07:00
1bfcf7574c
[test] validate region and single syntax
2024-07-01 20:33:28 -07:00
28e3cb799e
[test] update 2-clock arch and pcf
2024-06-29 17:40:20 -07:00
12c9686c27
[test] fixed some bugs on arch
2024-06-29 17:38:34 -07:00
5dd0549aed
[core] typo
2024-06-29 17:17:54 -07:00
bc2f02866d
[test] update testcase for 2-clk on programmable clock network
2024-06-29 17:17:05 -07:00
286df30947
[test] update clock arch xml syntax
2024-06-29 11:02:17 -07:00
67554cb8d8
[test] now use correct pcf for clock network testcases
2024-06-29 10:04:03 -07:00
8bc37080fa
[core] debuggging
2024-06-28 23:06:21 -07:00
1c69365938
[core] debugging
2024-06-28 18:17:38 -07:00
f4dd222c47
[test] deploy new testcases to basic reg tests
2024-06-28 13:45:36 -07:00
f1a4304ee7
[test] add new testcases for validate clock tree disable functions
2024-06-28 13:43:53 -07:00
ad5795bece
[test] add extra options to route clock rr_graph command in examples
2024-06-28 13:39:41 -07:00
cab649893b
[core] update clock architecture
2024-06-26 18:06:39 -07:00
c99178f350
[test] fixed a bug on pin locations
2024-06-25 12:34:52 -07:00
2cbb04b90d
[test] add a new testcase to validate programmable clock network with internal drivers
2024-06-25 11:58:05 -07:00
9bb076d892
[test] fixed a bug on pin mapping of tetbenche
2024-06-21 20:29:21 -07:00
292f4a9273
[test] fixed a bug where ace is no required
2024-06-21 18:43:25 -07:00
c2e759fa70
[arch] fixed some bugs
2024-06-21 18:42:29 -07:00
7d67b9d5b9
[test] deploy new tests to basic reg tests
2024-06-21 18:14:54 -07:00
8d7dba2d57
[test] add a new testcase to programmable clock network on supporting reset signals
2024-06-21 18:13:37 -07:00
6c5988575c
[test] update clock network testcase
2024-06-21 16:59:21 -07:00
4d9aacdf8f
[test] add and deploy new benchmark
2024-06-02 14:27:02 -07:00
ad2d101554
[test] deploy new benchmarks
2024-06-02 14:23:08 -07:00
8f2974d7a1
[test] update golden copies
2024-05-29 10:31:19 -07:00
3c49af6a08
[test] code format
2024-05-20 21:28:46 -07:00
f25081eb31
[test] add a new test to validate ecb when tile modules are used
2024-05-20 21:10:49 -07:00
852b01aaff
[test] rework
2024-05-20 17:20:04 -07:00
a9a5fbee34
[test] add fully connected feedback connections to directlist
2024-05-20 17:02:20 -07:00
807c37d3ff
[test] fixed some bugs
2024-05-20 13:47:22 -07:00
6146d0be9f
[arch] Move clb I to right side as left side is not supported yet
2024-05-20 13:43:04 -07:00
65dd342c60
[arch] typo
2024-05-20 12:11:22 -07:00
653521755b
[test] add new testcase for ecb to basic regtest
2024-05-20 12:09:12 -07:00
bdc13e491e
[arch] adding openfpga arch for ecb
2024-05-20 12:04:52 -07:00
c795dd2f1a
[arch] adding a new arch where feedback loops are modelled by direct connections
2024-05-20 12:00:39 -07:00
65a8db4f38
[arch] replace out-of-date keywords
2024-05-20 11:18:46 -07:00
372e386330
[test] add new tests to verify rr graph preloading in two file formats
2024-05-09 23:10:45 -07:00
b8b8fb6d3b
[test] update golden files
2024-05-07 13:25:23 -07:00
81730da7b2
[test] update golden files
2024-05-07 13:25:04 -07:00
e72d71fe28
[test] update golden outputs
2024-05-07 13:24:45 -07:00
deee75f828
[test] use a different W to avoid vvp collapse
2024-05-07 12:20:58 -07:00
7a0cd764d3
[test] fixed some bugs
2024-05-07 11:23:33 -07:00
13f8dd096e
[test] create a new example script for fixed routing W case
2024-05-07 10:24:15 -07:00
00f39d55ab
[test] now use fixed routing channel width
2024-05-06 23:32:27 -07:00
3615bdceeb
[test] avoid no-fanin errors for hetero arch
2024-05-06 15:32:27 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
c334a0a792
[test] fixed a bug and add golden outputs
2024-05-02 22:07:22 -07:00
98006608c2
[test] add fabric hierarchy file to golden outputs
2024-05-02 22:03:23 -07:00
4e3bbbe45e
[test] add options to write fabric hierarchy file
2024-05-02 22:00:47 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
1af8a4ae4f
[test] add golden outputs
2024-04-11 15:20:34 -07:00
9b0a491819
[test] now validate no time stamp file for fabric pin physical location
2024-04-11 15:16:34 -07:00
d51832a4e2
[ci] typo
2024-04-11 15:13:20 -07:00
e85df6dcfd
[ci] deploy new tests to basic reg tests
2024-04-11 15:11:41 -07:00
20ba0e1dd5
[test] add new testcases to validate options of write_fabric_pin_physical_location
2024-04-11 15:06:50 -07:00
0c680ec426
[test] now test regex as module name for fabric pin physical location
2024-04-11 15:01:19 -07:00
4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
c63cee458b
[script] adapt code format for python
2024-04-10 12:58:05 -07:00
3824b006cc
[test] add new golden outputs
2024-03-29 12:06:00 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
20386945bd
[test] add a new testcase to validate dump waveform
2024-03-29 11:53:55 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
2bd60dad11
[script] now timing extraction focus on the last found results
2023-12-12 14:10:13 -08:00
592e2e310c
[script] typo
2023-12-12 13:45:23 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
c5cc05a9f5
[script] add a new example default tool path config with a focus on timing
2023-12-12 13:22:50 -08:00
f689ef7654
[script] format
2023-12-12 13:15:03 -08:00
4c0f6e2273
[script] syntax
2023-12-12 13:14:47 -08:00
e753e6d22c
[script] syntax
2023-12-12 13:13:51 -08:00
d9db78ac30
[script] now run fpga task has a new option ``default_tool_path``
2023-12-12 13:11:48 -08:00
1a4aaaf759
[script] update openfpga flow to support args for default tool path
2023-12-12 10:00:50 -08:00
a7b22163a8
[script] fixe the mismatch on keywords against latest vpr
2023-12-12 09:52:42 -08:00
5c839c1858
[test] debug
2023-12-08 13:52:52 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
99f1c5493c
[test] add a new testcase to support vcs
2023-12-08 13:45:23 -08:00
a1169beaf0
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:34:49 -08:00
7475a002b6
Update repack_design_constraints.xml by changing the separater between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:33:55 -08:00
6055a42196
add test case
2023-12-01 03:04:32 -08:00
dff03e7993
[test] enable missing options in the arch used by benchmark sweeping tests
2023-11-14 09:45:02 -08:00
0b473e3454
[test] fixed the bug in single-mode lut testcase
2023-11-14 09:35:26 -08:00
d108284105
[test] update arch to keep golden outputs
2023-11-14 09:31:07 -08:00
913434b70d
[test] fixed the bug that golden netlists are modified
2023-11-14 09:28:57 -08:00
59d086a27f
[test] try to keep the golden inputs
2023-11-14 09:25:45 -08:00
1b8748abb4
[core] update vtr
2023-11-13 14:21:34 -08:00
d78f18d235
[test] add new testcase
2023-11-13 14:11:34 -08:00
8e875f3453
[test] add a new test case to validate the new feature
2023-11-02 21:08:36 -07:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
60b8c396dc
[test] add a new test
2023-09-25 21:25:21 -07:00
a4f53c64c6
[test] fixed a bug
2023-09-25 19:28:19 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
a1ed277a88
[test] typo
2023-09-23 15:12:02 -07:00
00e1a5df11
[test] fixed some bugs
2023-09-23 12:44:47 -07:00
195aa7a9a8
[test] developing new test to increase coverage on module renaming
2023-09-23 12:40:20 -07:00
f3279bd885
[test] now use 4x4 fabric to check the using index netlists
2023-09-20 22:49:47 -07:00
eeb1bd6662
[core] fixed some bugs
2023-09-17 23:16:15 -07:00
3fd60a165d
[test] typo
2023-09-17 17:42:15 -07:00
11e976ec92
[test] add a new test to validate renaming on fpga top/core modules
2023-09-17 17:38:37 -07:00
0ef1e0bde5
[test] add a new test to validate renaming rules
2023-09-17 13:29:12 -07:00
559fa45d89
[test] add a new test to validate module renaming using index
2023-09-16 17:55:52 -07:00
1287097ce5
[test] update golden netlists
2023-09-06 22:51:38 -07:00
401f8098a6
[test] update golden copies
2023-09-06 17:35:03 -07:00
db0bb291c2
[test] update settings
2023-08-22 15:22:48 -07:00
56cedf6c8b
[test] added a new test case to validate the support on different wire segment distribution on X and Y
2023-08-22 11:20:14 -07:00
1b132fd667
[test] add a new testcase to validate the support on different routing channel width on X and Y
2023-08-22 11:06:12 -07:00
15a8d8a76a
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
2023-08-18 21:59:06 -07:00
5f6050d404
[test] add a new test to validate combo: group tile, tile annotation and subtile
2023-08-18 21:48:40 -07:00
e4c5265b68
[test] arch syntax
2023-08-18 21:40:56 -07:00
5ac8919ce0
[test] add a new testcase to validate subtile with tile annotations
2023-08-18 21:37:15 -07:00
f69520d0c3
[arch] format
2023-08-18 11:15:25 -07:00
170a49c34f
[test] fix a bug in arch file
2023-08-18 11:15:05 -07:00
e82e4f487e
[test] add a new test to validate io subtile support
2023-08-18 11:13:34 -07:00
4afd48d930
[test] format
2023-08-17 15:33:09 -07:00
463897f78e
[test] fixed a bug in arch
2023-08-17 15:28:59 -07:00
3ac3eb4624
[test] adding more flavor to the L shape
2023-08-17 15:08:27 -07:00
913c232556
[test] deploy new test to basic reg test
2023-08-17 14:54:24 -07:00
85bc890009
[test] add a new test to validate comb options of group tile, group config block and L shape fabric
2023-08-17 14:52:30 -07:00
2f49c25f09
[test] updated
2023-08-11 21:19:06 -07:00
b155e660ee
[test] fixed a bug
2023-08-11 16:55:35 -07:00
16f102f4c1
[test] deploy new tests to basic regression tests
2023-08-11 13:07:41 -07:00
253d5fa26c
[core] a new test to validate the L shape in homo geneous fpga
2023-08-11 13:05:46 -07:00
dc0eec8b81
[test] added a new test to validate L shapre
2023-08-11 12:49:38 -07:00
0e9cf6e909
[test] added a new testcase to validate heterogeneous fpga using group config block
2023-08-06 22:11:38 -07:00
3e33f262bc
[test] added a new test to validate group_config_block support when fpga_core wrapper is enabled
2023-08-06 18:59:24 -07:00
46b1de08c6
[test] fixed a bug
2023-08-05 22:07:46 -07:00
b7048d3dc8
[test] adding new tests to validate group config block
2023-08-03 22:30:41 -07:00
667c5f8944
[test] fixed a bug on the testcase
2023-07-27 22:02:28 -07:00
952e84fce1
[test] now heterogeneous testcases for tile modules pass
2023-07-27 20:30:32 -07:00
beaa687a20
[core] fixed bugs on supporting heterogeneous blocks in tile modules
2023-07-27 20:29:18 -07:00
3d56bd0ff2
[test] deploy the new test to ci
2023-07-27 17:03:55 -07:00
65995d7c13
[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
2023-07-27 17:03:02 -07:00
46e58a56cb
[test] added a new test case to validate clock network when using the tile modules
2023-07-27 16:39:48 -07:00
81d699a723
[test] added a new testcase to validate carry chain connections in tile modules
2023-07-27 16:18:30 -07:00
e9f2adf3f9
[test] add a new testcase to validate carry chain connections when using tile modules
2023-07-27 16:06:43 -07:00
1ea8a33d4b
[test] add a new testcase to validate global tile connections on tile modules
2023-07-27 15:57:38 -07:00
a2848940df
[test] add a new testcase to ease debugging
2023-07-26 22:32:03 -07:00
5685fbd5e8
[test] adding a new test case to validate the tile modules on 4x4 fabric
2023-07-26 22:17:39 -07:00
bb837f4f79
[test] update golden netlists
2023-07-25 23:39:59 -07:00
0db4ef62e8
[test] add a new test for tile-based fabric: using preconfig testbenches
2023-07-25 15:48:14 -07:00
tangxifan
chungshien
Yitian4Debug
ubuntu