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338 Commits

Author SHA1 Message Date
Eddie Hung f858219c4e Cleanup tests 2020-02-27 10:17:29 -08:00
Alberto Gonzalez 2c2f092c90
Change attribute search value to specify precise location instead of simple line number. 2020-02-24 01:39:36 +00:00
Eddie Hung 1d401a7991 clean: ignore specify-s inside cells when determining whether to keep 2020-02-19 10:45:10 -08:00
Eddie Hung d20c1dac73 verilog: ignore ranges too without -specify 2020-02-13 17:58:43 -08:00
Eddie Hung 6b58c1820c verilog: improve specify support when not in -specify mode 2020-02-13 13:27:15 -08:00
Eddie Hung 2e51dc1856 verilog: ignore '&&&' when not in -specify mode 2020-02-13 13:06:13 -08:00
Eddie Hung b523ecf2f4 specify: system timing checks to accept min:typ:max triple 2020-02-13 12:42:15 -08:00
Eddie Hung 7cfdf4ffa7 verilog: fix $specify3 check 2020-02-13 12:42:04 -08:00
N. Engelhardt e069259a53
Merge pull request #1679 from thasti/delay-parsing 
Fix crash on wire declaration with delay
 2020-02-13 12:01:27 +01:00
Stefan Biereigel 90c78f1f85 add testcase for #1614 2020-02-03 21:29:54 +01:00
David Shah ebe1d7d5ab sv: More tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 7e741714df hierarchy: Correct handling of wildcard port connections with default values 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah a210675d71 sv: Add tests for wildcard port connections 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-02 16:12:33 +00:00
David Shah 9f5613100b
Merge pull request #1647 from YosysHQ/dave/sprintf 
ast: Add support for $sformatf system function
 2020-02-02 14:53:46 +00:00
Eddie Hung 136842b1ef Merge branch 'master' into eddie/submod_po 2020-02-01 02:14:19 -08:00
Eddie Hung d004953772 Add "help -all" and "help -celltypes" sanity test 2020-01-28 18:11:34 -08:00
Eddie Hung 3d9737c1bd Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-21 16:27:40 -08:00
Eddie Hung cd8f55a911 write_xaiger: fix for (* keep *) on flop output 2020-01-21 09:43:04 -08:00
David Shah 22c967e35e ast: Add support for $sformatf system function 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-19 21:20:17 +00:00
Eddie Hung 6a163b5ddd xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung fc4b8b8991 Remove submod changes 2019-12-30 14:56:14 -08:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
N. Engelhardt abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
Eddie Hung 151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung 705e520a52 Add a quick testcase for unknown modules as inout 2019-12-09 13:14:46 -08:00
Eddie Hung c61186dd9d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-27 13:24:03 -08:00
Eddie Hung ff1e357682 Add multiple driver testcase 2019-11-27 13:22:26 -08:00
Eddie Hung 6338615aa1 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-27 01:02:16 -08:00
Eddie Hung 8c813632b6 Revert "submod to bitty rather bussy, for bussy wires used as input and output" 
This reverts commit cba3073026.
 2019-11-27 00:48:22 -08:00
Eddie Hung 6318e3ce6d Fix wire width 2019-11-26 23:38:49 -08:00
Eddie Hung dd317c9280 Add testcase where \init is copied 2019-11-25 16:07:35 -08:00
Eddie Hung b46e636c91 Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff 2019-11-23 08:38:48 -08:00
Eddie Hung d223e11a72 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 22:28:35 -08:00
Eddie Hung 5cd3d3db0a Remove redundant flatten 2019-11-22 22:28:10 -08:00
Eddie Hung 08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung 2c5dfd802d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:24:45 -08:00
Eddie Hung 4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung 0806b8e398 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 16:50:56 -08:00
Eddie Hung 8779faf789 Cleanup spacing 2019-11-22 16:50:09 -08:00
Eddie Hung 2ef2e2c040 Add testcase 2019-11-22 16:48:11 -08:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung 6841e3b1c2 Another sloppy mistake! 2019-11-21 16:33:20 -08:00
Eddie Hung fe36275234 Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff 2019-11-21 16:32:52 -08:00
Eddie Hung 39fdcb892b async2sync -> clk2fflogic 2019-11-21 16:27:34 -08:00
David Shah 49b670ca38 sv: Add tests for SV always types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-21 21:06:28 +00:00
Eddie Hung 1cc106452f Add a equiv test too 2019-11-19 17:05:14 -08:00
Marcin Kościelnicki 15232a48af Fix #1462, #1480. 2019-11-19 08:57:39 +01:00
Marcin Kościelnicki 38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
Eddie Hung 045f344038 Use `sat -tempinduct` and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung b66c99ece0
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext 
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
 2019-09-18 12:40:08 -07:00
Eddie Hung f492567c87 Oops 2019-09-13 18:19:07 -07:00
Eddie Hung a2eee9ebef Add counter-example from @cliffordwolf 2019-09-13 16:41:10 -07:00
Eddie Hung 14d72c39c3 Revert "Make one check $shift(x)? only; change testcase to be 8b" 
This reverts commit e2c2d784c8.
 2019-09-13 16:33:18 -07:00
Eddie Hung bdb5e0f29c Cope with presence of reset muxes too 2019-09-11 13:36:37 -07:00
Eddie Hung f46ef47893 Add more tests 2019-09-11 13:22:41 -07:00
David Shah c43e52d2d7 Add equiv_opt -multiclock 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-11 13:55:59 +01:00
Eddie Hung 3a8582081e proc instead of prep 2019-09-11 00:14:06 -07:00
Eddie Hung 580faae8ad Add unsigned case 2019-09-11 00:07:17 -07:00
Eddie Hung 97e1520b13 Missing equiv_opt -assert 2019-09-06 22:50:03 -07:00
Eddie Hung e2c2d784c8 Make one check $shift(x)? only; change testcase to be 8b 2019-09-06 22:48:23 -07:00
Eddie Hung 51b559af2c Usee equiv_opt -assert 2019-09-06 22:48:04 -07:00
Eddie Hung ef0681ea4c simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select 2019-09-05 08:43:22 -07:00
Eddie Hung ba629e6a28 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-09-04 15:36:07 -07:00
Eddie Hung 0ca0706630 Expand test with `hierarchy' without -auto-top 2019-09-03 12:17:26 -07:00
Eddie Hung 8124716830 Add `read -noverific` before read 2019-09-03 10:52:34 -07:00
Eddie Hung d6a84a78a7 Merge remote-tracking branch 'origin/master' into eddie/deferred_top 2019-09-03 10:49:21 -07:00
Eddie Hung 4290548de3 Make abc9 test a bit more interesting 2019-08-30 20:31:53 -07:00
Eddie Hung 67587bad7f Add constant expression attribute to test 2019-08-29 09:10:20 -07:00
Eddie Hung 1fdb3fc98c Add failing test 2019-08-28 19:58:58 -07:00
Eddie Hung 78b7d8f531 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-23 11:32:44 -07:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung 66607845ec Remove Xilinx test 2019-08-22 16:18:07 -07:00
Eddie Hung e7a8cdbccf Add shregmap -tech xilinx test 2019-08-22 16:16:54 -07:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Clifford Wolf 1e3dd0a2da Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen 2019-08-19 13:04:06 +02:00
Eddie Hung e34f2de55d Merge remote-tracking branch 'origin/master' into clifford/testfast 2019-08-18 21:29:15 -07:00
Eddie Hung f5170a7eda Removal of more `stat` calls from tests 2019-08-18 21:28:45 -07:00
whitequark 101235400c
Merge branch 'master' into eddie/pr1266_again 2019-08-18 08:04:10 +00:00
Clifford Wolf 9e940f1276 Speed up "make test" and related cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:37:07 +02:00
Clifford Wolf f20be90436 Add test for pmtest_test "reduce" demo pattern 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-17 14:05:10 +02:00
Clifford Wolf 40c40d9f5d Do not use Verific in tests/various/write_gzip.ys 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 14:22:46 +02:00
Eddie Hung 12c692f6ed Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" 
This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
 2019-08-12 12:06:45 -07:00
Eddie Hung 88d5185596 Merge remote-tracking branch 'origin/master' into eddie/fix_1262 2019-08-11 21:13:40 -07:00
David Shah f9020ce2b3
Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" 2019-08-10 17:14:48 +01:00
Eddie Hung 8bf45f34c4 Remove dump call 2019-08-07 21:36:02 -07:00
Eddie Hung 2b6cdfb39f Move tests/various/opt* into tests/opt/ 2019-08-07 21:35:48 -07:00
Eddie Hung 35bf509603 Add testcase from removed opt_ff.{v,ys} 2019-08-07 21:31:32 -07:00
Eddie Hung 2d1b517b01 Add signed opt_expr tests 2019-08-06 15:40:30 -07:00
Eddie Hung 769c750c22 Add signed test 2019-08-06 15:38:43 -07:00
Eddie Hung 51b39219cd Move LSB tests from wreduce to opt_expr 2019-08-06 15:24:49 -07:00
Eddie Hung 26cb3e7afc Merge remote-tracking branch 'origin/master' into eddie/wreduce_add 2019-08-06 14:50:00 -07:00
David Shah 3a3da678ad Add test for writing gzip-compressed files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 17:43:04 +01:00
David Shah 933db0410e Add support for reading gzip'd input files 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-26 10:23:58 +01:00
Eddie Hung c926eeb43a Add another test 2019-07-19 14:02:46 -07:00
Eddie Hung 5bd088a686 Add one more test with trimming Y_WIDTH of $sub 2019-07-19 13:11:30 -07:00
Eddie Hung 415a2716df Be more explicit 2019-07-19 12:53:18 -07:00
Eddie Hung 4e9b1d36fa Add tests for sub too 2019-07-19 12:50:11 -07:00
Eddie Hung 3839bd50f2 Add test 2019-07-19 12:43:02 -07:00
Eddie Hung 41243a53b3 Update test with more accurate LUT mask 2019-07-12 21:00:59 -07:00
Clifford Wolf 9546ccdbd3 Fix tests/various/async FFL test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:44:39 +02:00
Clifford Wolf 5138621482 Improve tests/various/async, disable failing ffl test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:21:25 +02:00
Clifford Wolf c18b23f055 Add tests/various/async.{sh,v} 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:59 +02:00
Clifford Wolf 3dd92fcd15 Improve tests/various/run-test.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 20:58:28 +02:00
Eddie Hung de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell 
write_xaiger to treat unknown cell connections as keep-s
 2019-07-03 09:43:00 -07:00
Clifford Wolf e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf 1f173210eb Fix tests/various/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:25:05 +02:00
Clifford Wolf ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Eddie Hung 9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung 81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
Eddie Hung 90382a0f6d Update test too 2019-07-02 08:19:23 -07:00
Eddie Hung 04459cb30a Comment out invalid syntax 2019-06-30 11:48:01 -07:00
Eddie Hung 64f6b0c747 Try command in another module 2019-06-28 13:41:32 -07:00
Eddie Hung 2c6aaef3db Add test 2019-06-28 13:32:09 -07:00
Eddie Hung dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Eddie Hung 440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung 6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung 18acb72c05 Add #1135 testcase 2019-06-27 11:02:52 -07:00
Eddie Hung 3910bc2ea6 Copy tests from eddie/fix1132 2019-06-27 06:01:50 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Eddie Hung 9dca024a30 Add tests/various/abc9.{v,ys} with SCC test 2019-06-24 21:52:53 -07:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Eddie Hung 32f637ffdb Add more tests 2019-06-21 12:31:04 -07:00
Eddie Hung ae8305ffcc Fix testcase 2019-06-21 12:13:00 -07:00
Eddie Hung 6ec8160981 Add more muxpack tests, with overlapping entries 2019-06-21 11:45:53 -07:00
Eddie Hung 63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Eddie Hung 844c42cef8 Missing a `clean` and `opt_expr -mux_bool` in test 2019-06-20 19:47:59 -07:00
Eddie Hung 75375a3fbc Add test 2019-06-20 19:47:59 -07:00
Eddie Hung d0bbf9e4d4 Extend sign extension tests 2019-06-20 12:43:59 -07:00
Eddie Hung b77322034c Remove leftover comment 2019-06-20 10:15:04 -07:00
Eddie Hung b98276fa61 Add test 2019-06-20 10:13:52 -07:00
Clifford Wolf a8c85d1b4b Update some .gitignore files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 14:27:57 +02:00
Eddie Hung 45c2a5f876 Add shregmap -tech xilinx test 2019-06-12 08:34:06 -07:00
Eddie Hung c314ca3c51 Add test 2019-06-10 16:16:26 -07:00
Eddie Hung 58f4b106f3 Merge branch 'master' into eddie/muxpack 2019-06-07 15:47:28 -07:00
Eddie Hung b959bf79c0 Add nonexcl case test, comment out two others 2019-06-07 15:35:15 -07:00
Eddie Hung 1da12c5071 Add @cliffordwolf freduce testcase 2019-06-07 12:12:11 -07:00
Eddie Hung e263bc249b Add nonexclusive test from @cliffordwolf 2019-06-07 11:54:29 -07:00
Eddie Hung 0f6e914ef6 Another muxpack test 2019-06-07 08:34:58 -07:00
Clifford Wolf a3bbc5365b Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983 2019-06-07 12:08:42 +02:00
Eddie Hung 5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung 0a66720f6f Fix warnings 2019-06-06 14:01:42 -07:00
Eddie Hung ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung 705388eb24 Add non exclusive test 2019-06-06 12:44:06 -07:00
Eddie Hung b8620f7b3d One more and tidy up 2019-06-06 12:03:44 -07:00
Eddie Hung 5d4eca5a29 Add a few more special case tests 2019-06-06 11:59:41 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
Maciej Kurc b79bd5b3ca Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-04 10:42:42 +02:00
Eddie Hung f3e86e06e6 Fix init 2019-05-24 18:43:26 -07:00
Eddie Hung e1cb1bb948 Fix typos 2019-05-24 18:34:27 -07:00
Eddie Hung d15da4bc11 Add more tests 2019-05-24 18:33:18 -07:00
Eddie Hung 4bd9465ed3 Call proc 2019-05-24 18:32:02 -07:00
Eddie Hung f0c6b73b72 Fix duplicate driver 2019-05-24 17:44:57 -07:00
Eddie Hung 47f9ea142f Add opt_rmdff tests 2019-05-23 11:26:38 -07:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf d97c644bc1 Add tests/various/chparam.sh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 16:03:15 +02:00
Clifford Wolf 8c6e94d57c Improve tests/various/specify.ys 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 12:26:15 +02:00
Eddie Hung 554c58715a More testing 2019-05-03 15:54:25 -07:00
Eddie Hung bfb8b3018b Fix spacing 2019-05-03 15:42:02 -07:00
Eddie Hung 09841c2ac1 Add quick-and-dirty specify tests 2019-05-03 15:35:26 -07:00
Udi Finkelstein ac10e7d96d Initial implementation of elaboration system tasks 
(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
 2019-05-03 03:10:43 +03:00
Clifford Wolf a80e74dc20 Updaye pmux2shiftx test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 16:17:43 +02:00
Clifford Wolf a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx 
Add pmux2shiftx command
 2019-04-22 08:39:37 +02:00
Clifford Wolf d38f0c1a96 Fix tests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:20 +02:00
Clifford Wolf b3a3e08e38 Improve "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 02:03:44 +02:00
Clifford Wolf 37728520a6 Improvements in "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 01:15:48 +02:00
Clifford Wolf 0070184ea9 Improvements in pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 4c831d72ef Add test for pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Eddie Hung b3378745fd
Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
Eddie Hung 7685469ee2 Add default entry to testcase 2019-04-11 15:03:40 -07:00
Jim Lawson 71bcc4c644 Address requested changes - don't require non-$ name. 
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
 2019-02-22 16:06:10 -08:00
Jim Lawson 5c4a72c43e Fix normal (non-array) hierarchy -auto-top. 
Add simple test.
 2019-02-19 14:35:15 -08:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein 80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
Clifford Wolf 724cead61d Added "pmuxtree" command 2015-04-07 20:27:10 +02:00
Clifford Wolf 01ef34c147 Added tests/various/constmsk_test.ys 2014-09-04 15:07:30 +02:00
Clifford Wolf d49dec1f86 Added tests/various/.gitignore 2014-07-26 17:43:41 +02:00
Clifford Wolf b21ebe1859 Added tests/various/submod_extract.ys 2014-07-26 17:22:18 +02:00