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527 Commits

Author SHA1 Message Date
Clifford Wolf 22aabe05c9 Verbose reading of liberty and constr files in ABC pass 2014-03-09 15:15:38 +01:00
Clifford Wolf e3b11ea2d6 Fixed bug in freduce command 2014-03-07 18:44:23 +01:00
Clifford Wolf 6f8865d81a Some minor code cleanups in freduce command 2014-03-07 18:29:04 +01:00
Clifford Wolf 54d74cf616 Added freduce -dump 2014-03-06 22:06:58 +01:00
Clifford Wolf da5859a674 Added freduce -stop 2014-03-06 18:14:26 +01:00
Clifford Wolf 9b9c3327cc Fixed undef handling in opt_reduce 2014-03-06 14:18:34 +01:00
Clifford Wolf 1ecaf1bb76 Added techmap -max_iter option 2014-03-06 12:15:17 +01:00
Clifford Wolf 96e753041d fixed freduce for Minisat::SimpSolver: use frozen_literal() 2014-03-03 02:14:27 +01:00
Clifford Wolf 9e99984336 Fixed const folding of $bu0 cells 2014-02-27 04:09:32 +01:00
Clifford Wolf 548519875b Fixed bug (typo) in passes/opt/opt_const.cc 2014-02-22 17:07:22 +01:00
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap 2014-02-20 23:42:07 +01:00
Clifford Wolf 737b71c735 Added "extract -ignore_parameters" and "extract -ignore_param ..." 2014-02-20 23:31:13 +01:00
Clifford Wolf 236fc4209c Added "extract -map %<design_name>" 2014-02-20 23:30:15 +01:00
Clifford Wolf 483c99fe46 Added "design -push" and "design -pop" 2014-02-20 23:28:59 +01:00
Clifford Wolf 0dadfed46d Added connwrappers command 2014-02-20 20:44:11 +01:00
Clifford Wolf 23a3b488a0 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-18 20:05:53 +01:00
Clifford Wolf a71d09421d Added techmap support for _TECHMAP_CONNMAP_*_ 2014-02-18 19:51:00 +01:00
Clifford Wolf a78bba1f5c Added "sat -dump_cnf" 2014-02-18 09:29:08 +01:00
Clifford Wolf 32af10fa9b Coding style corrections in SatHelper::dump_model_to_vcd() 2014-02-18 09:28:05 +01:00
Clifford Wolf 13051e6acf Added "sat -initsteps" 2014-02-18 09:03:16 +01:00
Clifford Wolf 0851c2b6ea Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups 2014-02-17 13:59:39 +01:00
Andrew Zonenberg 4a948d780a Added "-dump_fail_to_vcd" argument to SAT solver 2014-02-17 13:52:36 +01:00
Clifford Wolf ca53ef5098 Better preserve wires when flattening (in comparison to techmap) 2014-02-17 09:44:39 +01:00
Clifford Wolf 6d63f39eb6 Added some additional checks to techmap 2014-02-16 22:18:06 +01:00
Clifford Wolf a9b11d7c83 Added CONSTMSK and CONSTVAL feature to techmap 2014-02-16 21:58:59 +01:00
Clifford Wolf 28e14ee50a Fixed handling of "keep" attribute on wires in opt_clean 2014-02-16 21:58:27 +01:00
Clifford Wolf 42ce3db983 Fixed use of selection in splitnets command 2014-02-16 17:39:50 +01:00
Clifford Wolf d3dc22a90f Added recursion support to techmap 2014-02-16 17:16:44 +01:00
Clifford Wolf 9a816b65a8 Added != support for relational select pattern 2014-02-16 00:16:54 +01:00
Clifford Wolf 623a68f528 Added iopadmap -bits 2014-02-15 21:59:26 +01:00
Clifford Wolf cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff 2014-02-15 16:34:12 +01:00
Clifford Wolf 67effc9f5b Fixed opt_const handling of double invert with non-1 output width 2014-02-15 13:16:08 +01:00
Clifford Wolf 3121d19d95 Added abc -keepff option 2014-02-14 11:28:42 +01:00
Clifford Wolf de3ea9269a updated default ABC command strings 2014-02-13 19:14:15 +01:00
Clifford Wolf a123941618 Updated ABC 2014-02-13 18:56:36 +01:00
Clifford Wolf cd9e8741a7 Implemented read_verilog -defer 2014-02-13 13:59:13 +01:00
Clifford Wolf b463907890 Removed double blanks in ABC default command sequences 2014-02-13 08:12:52 +01:00
Clifford Wolf 7664f5d92b Updated ABC and some related changes 2014-02-13 08:07:08 +01:00
Clifford Wolf ab71bd0746 Updated ABC to rev e97a6e1d59b9 2014-02-12 08:35:42 +01:00
Clifford Wolf 38469e7686 Various improvements in expose command (added -sep and -cut) 2014-02-09 11:07:46 +01:00
Clifford Wolf b6f33576d5 Added delete {-input|-output|-port} 2014-02-09 10:03:26 +01:00
Clifford Wolf b3b5fac191 Bugfix in delete command 2014-02-09 09:34:58 +01:00
Clifford Wolf 85914c36e5 Fixed handling of async reset in expose -evert-dff 2014-02-08 21:26:40 +01:00
Clifford Wolf db86aaa07d Build fixes for log cmd 2014-02-08 21:21:51 +01:00
Clifford Wolf c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-08 21:08:46 +01:00
Clifford Wolf 0935e20003 Implemented expose -evert-dff 2014-02-08 21:08:38 +01:00
Johann Glaser af14bb5f65 added "log" command 2014-02-08 19:19:32 +01:00
Clifford Wolf 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect 2014-02-08 19:13:19 +01:00
Clifford Wolf 926fa61119 Added various new options to splice command 2014-02-08 16:37:18 +01:00
Clifford Wolf 0c11d04144 Added %a select operator 2014-02-08 16:31:38 +01:00
Clifford Wolf 6644f80d97 Moved some passes to other source directories 2014-02-08 14:39:15 +01:00
Clifford Wolf 03ee63ff80 Added support for "keep" attribute to abc pass 2014-02-08 14:25:29 +01:00
Clifford Wolf 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) 2014-02-08 14:21:34 +01:00
Clifford Wolf 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean 2014-02-08 14:21:04 +01:00
Clifford Wolf 2c51619c2b Now also move net labes to the right position in splice cmd 2014-02-08 00:06:00 +01:00
Clifford Wolf 274bcef66c Improved detection of primary wire for a signal in opt_clean 2014-02-07 23:50:17 +01:00
Clifford Wolf 244e8ce1f4 Added splice command 2014-02-07 20:30:56 +01:00
Clifford Wolf 08aa1062b4 Added log_header() to splitnets 2014-02-07 19:51:15 +01:00
Clifford Wolf fc3b3c4ec3 Added $slice and $concat cell types 2014-02-07 17:44:57 +01:00
Clifford Wolf 99b1e9ee56 Re-enabled abc "retime" after sorting yout the yosys-bigsim problem 2014-02-07 16:36:37 +01:00
Clifford Wolf 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc 2014-02-07 14:16:42 +01:00
Clifford Wolf 0192f1c66e Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed) 2014-02-06 22:31:58 +01:00
Clifford Wolf 58cb8d65af Added "retime" to standard ABC recipes 2014-02-06 22:16:20 +01:00
Clifford Wolf 91eab69912 Added copy command 2014-02-06 22:09:21 +01:00
Clifford Wolf cf593222f2 Added design -stash/-copy-from/-copy-to 2014-02-06 21:52:07 +01:00
Clifford Wolf 37fdb2ca7a Added support for s: select expressions (wire width) 2014-02-06 19:45:03 +01:00
Clifford Wolf 9428050dd6 Added i:, o:, and x: selection pattern 2014-02-06 19:35:33 +01:00
Clifford Wolf d7d1c7baf8 Added support for %m selection op 2014-02-06 19:30:08 +01:00
Clifford Wolf f2fdcef13d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-06 19:22:50 +01:00
Clifford Wolf fa295a4528 Added generic RTLIL::SigSpec::parse_sel() with support for selection variables 2014-02-06 19:22:46 +01:00
Johann Glaser 34eb77d2bf new %s: add sub-modules to selection 2014-02-06 17:36:39 +01:00
Clifford Wolf d4b0f28881 Added support for sat -show @<sel_name> 2014-02-06 17:32:51 +01:00
Clifford Wolf b1a12c5f37 Added sat -set-init-def and sat -tempinduct-def 2014-02-06 16:15:23 +01:00
Clifford Wolf 594d52e0b6 Added opt_const -undriven 2014-02-06 15:49:03 +01:00
Clifford Wolf c526e56747 Added expose -dff 2014-02-06 15:48:42 +01:00
Clifford Wolf c13c5b9b7b Changed techmap description from "simple" to "generic" 2014-02-06 13:10:06 +01:00
Clifford Wolf eb8fd4a163 Added miter -make_outcmp 2014-02-06 02:20:55 +01:00
Clifford Wolf 80a1cdb0e2 Added sat -set-init-zero support 2014-02-06 01:40:01 +01:00
Clifford Wolf e915043144 Added sat -verify and -falsify support for non-prove cases 2014-02-06 00:59:41 +01:00
Clifford Wolf cd06055e77 Added expose command 2014-02-05 23:59:55 +01:00
Clifford Wolf dbfcc2f4e2 Simplified select "Assertation failed" message generation 2014-02-05 18:52:55 +01:00
Clifford Wolf 94b802c65d Merge branch 'master' of github.com:cliffordwolf/yosys 2014-02-05 18:46:47 +01:00
Clifford Wolf f6e6e9b844 Added selection support for r: and selection with relational operators 2014-02-05 18:24:45 +01:00
Johann Glaser 3c0b5139a1 be more verbose for select -assert-any and -assert-none 2014-02-05 16:03:02 +01:00
Johann Glaser 667543de0b improved help for "select" 2014-02-05 15:53:02 +01:00
Clifford Wolf 5bf33de24a Added setattr and setparam commands 2014-02-05 11:11:55 +01:00
Clifford Wolf 1fb8ba73bd Throw errors if non-existing selection variables are used 2014-02-04 23:31:06 +01:00
Clifford Wolf b1bf55dd63 Added select -none 2014-02-04 23:23:44 +01:00
Clifford Wolf 99b9c56da1 Fixed detection of init attribute in opt_rmdff 2014-02-04 23:00:32 +01:00
Clifford Wolf 69e867f3e8 Added support for inline commands to abc -script 2014-02-04 22:01:53 +01:00
Clifford Wolf 7a5f378bae Added hierarchy -purge_lib option 2014-02-04 16:50:13 +01:00
Clifford Wolf 6891fd79a3 added sat -falsify 2014-02-04 13:34:37 +01:00
Clifford Wolf d267bcde4e Fixed bug in sequential sat proofs and improved handling of asserts 2014-02-04 12:46:16 +01:00
Clifford Wolf ecdf1f5577 Improved handling of reg init in opt_share and opt_rmdff 2014-02-04 12:02:47 +01:00
Clifford Wolf 9e35021585 Addred sat option -ignore_unknown_cells 2014-02-03 16:26:10 +01:00
Clifford Wolf a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) 2014-02-03 13:01:45 +01:00
Clifford Wolf de336d93b2 More opt_const -mux_bool features 2014-02-02 22:41:24 +01:00
Clifford Wolf 9d0b69edaa Added opt_const -mux_bool 2014-02-02 22:11:08 +01:00
Clifford Wolf bee4450c4c Added support for inverter chains to opt_const 2014-02-02 21:46:42 +01:00
Clifford Wolf 67b0ce2578 Only generate write-enable $and if WE is not constant 1 in memory_map 2014-02-02 21:27:26 +01:00
Clifford Wolf 83fa652820 Added constant-clock case to opt_rmdff 2014-02-02 21:09:08 +01:00
Clifford Wolf aa732b0c73 Added show -notitle option 2014-02-02 17:55:32 +01:00
Clifford Wolf 9808acdc75 Added delete command 2014-02-02 17:11:19 +01:00
Clifford Wolf a9e2d86f86 Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax 2014-02-02 16:47:17 +01:00
Clifford Wolf f4f0bd6eef Fixed a bug in miter command 2014-02-01 22:53:27 +01:00
Clifford Wolf 374674aff4 Added sat -show-inputs and -show-outputs 2014-02-01 22:52:44 +01:00
Clifford Wolf caf540d1ad Added show -color support for cells and finished show -label implementation 2014-02-01 18:23:32 +01:00
Clifford Wolf fa92722358 Added miter command 2014-02-01 10:35:56 +01:00
Johann Glaser e9a2094774 enabled multiple "-map" for the extract pass 2014-01-25 21:11:34 +01:00
Clifford Wolf c1ed2607fb Added support for // comments in liberty parser 2014-01-25 06:32:16 +01:00
Clifford Wolf 32a91458a7 Added hilomap command 2014-01-19 21:58:58 +01:00
Clifford Wolf 03a876c7e8 Added sat -tempinduc and sat -prove-asserts 2014-01-19 16:35:17 +01:00
Clifford Wolf 1e67099b77 Added $assert cell 2014-01-19 14:03:40 +01:00
Clifford Wolf 839af272ad Improved setundef random number generator 2014-01-18 02:56:36 +01:00
Clifford Wolf 091d9abc3e Added setundef command 2014-01-17 23:14:36 +01:00
Clifford Wolf 2e370d5a2f Added support for $adff with undef data inputs to opt_rmdff 2014-01-17 16:42:40 +01:00
Clifford Wolf 651ce67d97 Added select -assert-none and -assert-any 2014-01-17 16:34:50 +01:00
Clifford Wolf f3154f5694 Added automatic memid generation to memory_unpack command 2014-01-17 00:15:15 +01:00
Clifford Wolf 4d8318ad1b Added memory_unpack command 2014-01-17 00:05:02 +01:00
Martin Schmölzer aa17f16fec Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3)) 
This fixes compilation errors on Arch Linux.

Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
 2014-01-14 20:12:45 +01:00
Clifford Wolf 0c5b1f32d4 Added hierarchy -libdir option 2014-01-14 19:28:20 +01:00
Clifford Wolf 9a00980129 renamed LibertyParer to LibertyParser 2014-01-14 18:57:47 +01:00
Clifford Wolf c1da7661a5 Added "+" to list of liberty token characters 2014-01-14 18:56:29 +01:00
Clifford Wolf 54275c61ee Added "opt_const -mux_undef" 2014-01-14 11:10:29 +01:00
Clifford Wolf bc541b47ea Improved performance of freduce input cone reduction 2014-01-04 13:10:51 +01:00
Clifford Wolf b791af174e Improved freduce performance on const signals 2014-01-04 00:06:36 +01:00
Clifford Wolf 10f45b8c8e Performance improvements in freduce pass 2014-01-03 21:29:28 +01:00
Clifford Wolf c44e1bec6d More freduce cleanups 2014-01-03 18:17:28 +01:00
Clifford Wolf 03f0ab9de2 Cleanups in freduce command 2014-01-03 17:50:39 +01:00
Clifford Wolf 8a8d444648 Tiny cleanup in proc_mux.cc 2014-01-03 16:54:59 +01:00
Clifford Wolf 60fbca9970 Added "splitnets -driver" 2014-01-03 14:01:06 +01:00
Clifford Wolf bf5e5429c1 Use selection in freduce command 2014-01-03 13:15:11 +01:00
Clifford Wolf c3e9f0712f Another small freduce cleanup/bugfix 2014-01-03 12:34:18 +01:00
Clifford Wolf 914e208aa3 Added "connect" command 2014-01-03 12:33:00 +01:00
Clifford Wolf 67d155078d More freduce cleanups and bugfixes 2014-01-03 02:44:05 +01:00
Clifford Wolf fb2bf934dc Added correct handling of $memwr priority 2014-01-03 00:22:17 +01:00
Clifford Wolf 536e20bde1 Fixed more complex undef cases in freduce 2014-01-02 23:40:20 +01:00
Clifford Wolf 5a0f561d9c Now */ is optional in */<mode>:<arg> selections 2014-01-02 20:35:37 +01:00
Clifford Wolf 456ae31a8a Added "rename -hide" command 2014-01-02 20:23:34 +01:00
Clifford Wolf 0759c97748 More "freduce" related fixes and improvements 2014-01-02 19:37:34 +01:00
Clifford Wolf ced4d7b321 Added support for module->connections to select %ci, %co and %x handling 2014-01-02 18:44:24 +01:00
Clifford Wolf c6b33f81eb Some cleanups in freduce -inv mode (and switched from -noinv to -inv) 2014-01-02 18:11:01 +01:00
Clifford Wolf 249ef8695a Major rewrite of "freduce" command 2014-01-02 16:52:33 +01:00
Clifford Wolf e09ebf475c Fixed use of limited length buffer in ABC blif parser 2013-12-31 21:58:35 +01:00
Clifford Wolf 4892a3ce6d Added abc -dff and -clk support 2013-12-31 21:25:09 +01:00
Clifford Wolf be5dab87fd Now using BLIF as ABC input format 2013-12-31 14:29:29 +01:00
Clifford Wolf c616802ac7 Always use BLIF as ABC output format 2013-12-31 13:41:16 +01:00
Clifford Wolf bf607df6d5 Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen) 2013-12-29 17:39:49 +01:00
Clifford Wolf fe8ec32a1c Added new cell types to manual 2013-12-28 12:10:32 +01:00
Clifford Wolf c69c416d28 Added $bu0 cell (for easy correct $eq/$ne mapping) 2013-12-28 12:02:14 +01:00
Clifford Wolf 7f71787599 Added sat -prove-x and -set-def-inputs 2013-12-28 11:24:36 +01:00
Clifford Wolf bd39263796 Improved $_MUX_ handling in opt_const 2013-12-28 10:30:31 +01:00
Clifford Wolf d81e3ed3ae More conservastive $eq/$ne/$eqx/$nex opt_const code 2013-12-28 10:29:22 +01:00
Clifford Wolf c9699fe76d More $eq/$ne/$eqx/$nex fixes in opt_const 2013-12-27 15:18:14 +01:00
Clifford Wolf 7b02a44efb Fixed/improved opt_const $eq/$ne/$eqx/$nex handling 2013-12-27 14:21:24 +01:00
Clifford Wolf 369bf81a70 Added support for non-const === and !== (for miter circuits) 2013-12-27 14:20:15 +01:00
Clifford Wolf 11ffa78677 Added sat -set-def/-set-*-undef support 2013-12-27 13:27:21 +01:00
Clifford Wolf fb31d10236 Renamed sat -set-undef to -set-any-undef 2013-12-27 13:02:46 +01:00
Clifford Wolf 334b0cc803 Fixed dfflibmap for unused output ports 2013-12-21 20:47:22 +01:00
Clifford Wolf 8856cec308 Now prefer smallest cells in dfflibmap 2013-12-21 08:42:37 +01:00
Clifford Wolf 1fb29050e5 Cleanup of dfflibmap cellmap exploration code 2013-12-20 14:21:18 +01:00
Clifford Wolf eaf7d9675d Further improved dfflibmap cellmap exploration 2013-12-20 12:34:34 +01:00
Clifford Wolf 404bcc2d1e Fixed dfflibmap endless-loop bug 2013-12-20 12:13:51 +01:00
Clifford Wolf c904f5e197 Prefer non-inverted clocks in dfflibmap 2013-12-19 13:21:57 +01:00
Clifford Wolf 2b90ba1e96 Added sat -max_undef feature 2013-12-07 23:58:55 +01:00
Clifford Wolf 8a815ac741 Added "sat" undef support and "sat -set-init" options 2013-12-07 17:28:51 +01:00
Clifford Wolf 5de57e9970 Fixed compiler warining in passes/sat/eval.cc 2013-12-07 16:19:24 +01:00
Clifford Wolf 325b764341 Added eval -set-undef and eval -table 2013-12-07 11:58:22 +01:00
Clifford Wolf 06d96e8fcf Fixes in fsm detect/extract for better detection of non-fsm circuits 2013-12-06 12:53:20 +01:00
Clifford Wolf f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf 93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf 6e227e3666 Fixed submod for non-primitive cells 2013-12-02 12:53:55 +01:00
Clifford Wolf e881878341 Fixed submod for non-cleaned designs 2013-12-02 12:18:07 +01:00
Clifford Wolf 97efc2ed5f A fix in memory_dff for write ports with static addresses 2013-12-01 14:08:18 +01:00
Clifford Wolf 7295b25955 Progress on AppNote 011 2013-11-29 16:42:49 +01:00
Clifford Wolf c60aaf8fa3 Added pattern support to "ls" command 2013-11-28 21:34:41 +01:00
Clifford Wolf 293356e87c Improved ID matching scheme in select (and thus for all commands) 2013-11-28 21:13:16 +01:00
Clifford Wolf 792bbad448 Fixes and improvements in "show" command 2013-11-28 21:02:19 +01:00
Clifford Wolf 0e52f3fa01 Added "src" attribute to processes 2013-11-28 17:37:50 +01:00
Clifford Wolf 5af7f4db72 Added support for "show -pause" and "show -format dot" 2013-11-28 13:35:28 +01:00
Clifford Wolf 38e7fa6530 Tighter integration of ABC build 2013-11-27 09:08:35 +01:00
Clifford Wolf bc3cc88719 Started implementing undef support in "sat" command 2013-11-25 21:40:00 +01:00
Clifford Wolf 3d95047ce2 Bugfixes in new "stat" command 2013-11-25 21:08:34 +01:00
Clifford Wolf 4c7d6e63ec Added "stat" command 2013-11-25 20:43:57 +01:00
Clifford Wolf 61412d167f Improvements in satgen undef handling 2013-11-25 16:50:45 +01:00
Clifford Wolf bd65e67d8a Improvements in satgen undef handling 2013-11-25 15:12:01 +01:00
Clifford Wolf 8c3f4b3957 Started implementing undef handling in satgen 2013-11-25 04:51:33 +01:00
Clifford Wolf 76f7c10cfc Using simplemap mappers from techmap 2013-11-24 23:31:14 +01:00
Clifford Wolf 3ee33cbdaf Added simplemap pass 2013-11-24 22:52:30 +01:00
Clifford Wolf 8dafecd34d Added module->avail_parameters (for advanced techmap features) 2013-11-24 20:29:07 +01:00
Clifford Wolf 4011d47646 Added techmap -D and -I options 2013-11-24 20:04:48 +01:00
Clifford Wolf 20175afd29 Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
Clifford Wolf f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf 609caa23b5 Implemented correct handling of signed module parameters 2013-11-24 17:17:21 +01:00
Clifford Wolf 72b35e0b99 Fixed "flatten" top-module detection: Only use on fully selected designs 2013-11-24 14:10:46 +01:00
Clifford Wolf 28093d9dd2 Added "top" attribute to mark top module in hierarchy 2013-11-24 05:03:43 +01:00
Clifford Wolf 5f9c7fc6ea Improved handling of techmap special wires 2013-11-23 16:49:58 +01:00
Clifford Wolf 532091afcb Added more generic _TECHMAP_ wire mechanism to techmap pass 2013-11-23 15:58:06 +01:00
Clifford Wolf 295e352ba6 Renamed "placeholder" to "blackbox" 2013-11-22 15:01:12 +01:00