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527 Commits

Author SHA1 Message Date
Clifford Wolf 273383692a Added "test_cell" command 2014-07-29 22:07:41 +02:00
Clifford Wolf e6df25bf74 Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ 2014-07-29 21:12:50 +02:00
Clifford Wolf 77e2d39cd0 Allow "hierarchy -generate" for $__ cells 2014-07-29 16:35:13 +02:00
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
Clifford Wolf 397b00252d Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
Clifford Wolf 7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf 8b0f50792c Added techmap -extern 2014-07-27 21:31:18 +02:00
Clifford Wolf 5da343b7de Added topological sorting to techmap 2014-07-27 16:43:39 +02:00
Clifford Wolf 0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf 77a1462f2d Fixed bug in opt_clean 2014-07-27 15:13:29 +02:00
Clifford Wolf d07a871d35 Improved performance of opt_const on large modules 2014-07-27 14:50:25 +02:00
Clifford Wolf dbb3556e3f Fixed a bug in opt_clean and some RTLIL API usage cleanups 2014-07-27 13:19:05 +02:00
Clifford Wolf d878fcbdc7 Added log_cmd_error_expection 2014-07-27 12:05:50 +02:00
Clifford Wolf 49f72421d5 Using new obj iterator API in a few places 2014-07-27 11:32:42 +02:00
Clifford Wolf 10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf 4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf d68c993ed2 Changed more code to the new RTLIL::Wire constructors 2014-07-26 21:30:38 +02:00
Clifford Wolf 946ddff9ce Changed a lot of code to the new RTLIL::Wire constructors 2014-07-26 20:12:50 +02:00
Clifford Wolf 3f4e3ca8ad More RTLIL::Cell API usage cleanups 2014-07-26 16:14:02 +02:00
Clifford Wolf 97a59851a6 Added RTLIL::Cell::has(portname) 2014-07-26 16:11:28 +02:00
Clifford Wolf f8fdc47d33 Manual fixes for new cell connections API 2014-07-26 15:58:23 +02:00
Clifford Wolf b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf 4755e14e7b Added copy-constructor-like module->addCell(name, other) method 2014-07-26 00:38:44 +02:00
Clifford Wolf 2bec47a404 Use only module->addCell() and module->remove() to create and delete cells 2014-07-25 17:56:19 +02:00
Clifford Wolf 5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf 0520bfea89 Fixed memory corruption in "opt_reduce" pass 2014-07-25 12:49:51 +02:00
Clifford Wolf c4e4f79a2a Disabled cover() for non-linux builds 2014-07-25 12:27:36 +02:00
Clifford Wolf 91bf0c90c8 Improvements in "cover" command 2014-07-25 12:04:40 +02:00
Clifford Wolf 6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf 9962384d3e Added cover() calls to opt_const 2014-07-24 20:47:18 +02:00
Clifford Wolf 45b4154b37 Added "make SMALL=1" 2014-07-24 19:03:57 +02:00
Clifford Wolf b17d6531c8 Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
Clifford Wolf 2f54345cff Added "cover" command 2014-07-24 16:14:19 +02:00
Clifford Wolf 20a7965f61 Various small fixes (from gcc compiler warnings) 2014-07-23 20:45:27 +02:00
Clifford Wolf c094c53de8 Removed RTLIL::SigSpec::optimize() 2014-07-23 20:32:28 +02:00
Clifford Wolf a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf 4e802eb7f6 Fixed all users of SigSpec::chunks_rw() and removed it 2014-07-23 15:36:09 +02:00
Clifford Wolf ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf 260c19ec5a Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3 2014-07-23 09:34:47 +02:00
Clifford Wolf 4a6d234ec7 SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands 2014-07-22 23:11:36 +02:00
Clifford Wolf 65a939cb27 Fixed memory corruption with new SigSpec API in proc_mux 2014-07-22 22:54:39 +02:00
Clifford Wolf e7e30f1c86 fixed memory leak in fsm_opt 2014-07-22 22:52:57 +02:00
Clifford Wolf 28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf 4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf 137dbf3cf7 Added "opt_const -keepdc" 2014-07-21 21:38:55 +02:00
Clifford Wolf 1873480ca5 Added mul to mux conversion to "opt_const -fine" 2014-07-21 17:19:50 +02:00
Clifford Wolf 1241a9fd50 Added "opt_const -fine" and "opt_reduce -fine" 2014-07-21 16:34:16 +02:00
Clifford Wolf e035f1d886 Added opt_const support for simple identities 2014-07-21 14:41:02 +02:00
Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls 2014-07-21 12:42:02 +02:00
Clifford Wolf 1d88f1cf9f Removed deprecated module->new_wire() 2014-07-21 12:35:06 +02:00
Clifford Wolf 3cb61d03f8 Wider range of cell types supported in "share" pass 2014-07-21 12:18:29 +02:00
Clifford Wolf b49beab1f3 Use ezSAT::non_incremental() in "share" pass 2014-07-21 02:08:38 +02:00
Clifford Wolf 04fcb07213 Added support for resource sharing in mux control logic 2014-07-20 20:44:14 +02:00
Clifford Wolf 1ce5e83555 Added "select -assert-count" 2014-07-20 20:15:49 +02:00
Clifford Wolf e9506bb2da Supercell creation for $div/$mod worked all along, fixed test benches 2014-07-20 18:54:06 +02:00
Clifford Wolf ff28029fdb Fixed creation of shift supercells in "share" pass 2014-07-20 17:06:36 +02:00
Clifford Wolf 4c38ec1cc8 Added "miter -equiv -flatten" 2014-07-20 15:33:07 +02:00
Clifford Wolf 8d04ca7d22 Added call_on_selection() and call_on_module() API 2014-07-20 15:33:06 +02:00
Clifford Wolf 5b3ee7a072 Added "share" supercell creation 2014-07-20 15:01:17 +02:00
Clifford Wolf 7b98e46ac3 Added removing of always inactive cells to "share" pass 2014-07-20 13:24:36 +02:00
Clifford Wolf 8819493db4 Progress in "share" pass 2014-07-20 11:04:52 +02:00
Clifford Wolf 15fd615da5 Progress in "share" pass 2014-07-20 03:03:04 +02:00
Clifford Wolf 2278995bd8 Started to implement real resource sharing 2014-07-19 20:54:32 +02:00
Clifford Wolf efd9604dfb Improved memory_share log messages 2014-07-19 15:46:11 +02:00
Clifford Wolf e0a819dbe5 More verbose memory_share help message 2014-07-19 15:34:14 +02:00
Clifford Wolf 297a0962ea Added SAT-based write-port sharing to memory_share 2014-07-19 15:33:55 +02:00
Clifford Wolf 26f982ac0b Fixed bug in memory_share feedback-to-en code 2014-07-19 15:32:14 +02:00
Clifford Wolf e441f07d89 Added translation from read-feedback to en-signals in memory_share 2014-07-18 16:46:40 +02:00
Clifford Wolf 44f13aff92 Improved seeding of color rng in show command 2014-07-18 16:44:45 +02:00
Clifford Wolf a341931972 Only create collision detect logic in memory_share if necessary 2014-07-18 14:32:40 +02:00
Clifford Wolf ab4b26679f Added memory_share 2014-07-18 13:16:56 +02:00
Clifford Wolf 309ae98246 Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port 2014-07-18 10:28:45 +02:00
Clifford Wolf 1b00861d0a Improved opt_reduce handling of mem wr_en mux bits 2014-07-17 12:12:04 +02:00
Clifford Wolf b76bf05cda Added support for "blackbox" attribute to iopadmap 2014-07-17 08:59:07 +02:00
Clifford Wolf 64a6906cc4 Added support for "blackbox" attribute to flatten/techmap 2014-07-17 08:58:51 +02:00
Clifford Wolf d678b6533d improved opt_reduce for $mem/$memwr WR_EN multiplexers 2014-07-16 14:08:51 +02:00
Clifford Wolf 765f172211 Changes to "memory" pass for new $memwr/$mem WR_EN interface 2014-07-16 12:49:50 +02:00
Clifford Wolf 3b52121d32 now ignore init attributes on non-register wires in sat command 2014-07-05 11:18:38 +02:00
Clifford Wolf 1c85584fe5 Do not create $dffsr cells with no-op resets in proc_dff 2014-06-19 12:29:29 +02:00
Clifford Wolf 22a998903b Added %D and %c select commands 2014-06-14 16:19:32 +02:00
Clifford Wolf 744e518467 fixed cell array handling of positional arguments 2014-06-07 12:17:11 +02:00
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
Clifford Wolf 7020f7fc13 added tee cmd 2014-06-03 09:23:31 +02:00
Clifford Wolf 68c99bf734 Fixed log messages in memory_dff 2014-06-01 11:32:27 +02:00
Johann Glaser 278085fa01 added log_header to miter and expose pass, show cell type for exposed ports 2014-05-28 18:05:38 +02:00
Johann Glaser 684c85902d be more verbose when techmap yielded processes 2014-05-26 17:13:41 +02:00
Clifford Wolf 68c059565a Fixed bug in opt_reduce (see vloghammer issue_044) 2014-05-12 12:45:47 +02:00
Clifford Wolf f69b5800c9 fixed syntax error in dot file created by "show" command 2014-05-10 16:22:56 +02:00
Clifford Wolf 9a34486bfb Fixed performance problem in opt_mux with nets driven by many conflicting drivers 2014-03-19 10:05:01 +01:00
Clifford Wolf 34e54cda5b Small improvement in SAT log messages 2014-03-13 13:12:49 +01:00
Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Siesh1oo 8127d5e8c3 - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). 
This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems.
 - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
 2014-03-12 23:17:14 +01:00
Clifford Wolf 9087ece97c OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:52:37 +01:00
Clifford Wolf 91704a7853 Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys 
(see https://github.com/cliffordwolf/yosys/pull/28)
 2014-03-11 14:24:24 +01:00
Clifford Wolf fa75c8286e Fixed memory corruption in passes/abc/blifparse.cc 2014-03-11 13:09:01 +01:00
Clifford Wolf fcae92868d Fixed dumping of timing() { .. } block in libparse 2014-03-09 15:16:07 +01:00