riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,374 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

1114 Commits

Author SHA1 Message Date
tangxifan 5c4e749b95 [engine] add standalone vpr commands 2022-12-30 18:12:51 -08:00
tangxifan 90bbb50047 [script] rename shared library name for tcl, so that it is straightforward to load in tcl 2022-12-01 15:59:52 -08:00
tangxifan 338e191f77 [script] enable swig flags when compiling vtr 2022-12-01 15:16:58 -08:00
tangxifan 78d4991a4e [script] add missing flags required 2022-12-01 14:49:05 -08:00
tangxifan 33b400de39 [script] compilation passed but failed when loading .so to tclsh 2022-12-01 13:51:50 -08:00
tangxifan 819b716260 [script] debugging 2022-12-01 12:30:57 -08:00
tangxifan 2e585024f7 [script] debugging 2022-12-01 12:26:30 -08:00
tangxifan 48a9a97562 [script] enabling swig in cmake compilation 2022-12-01 12:23:01 -08:00
tangxifan 0574efa9b3 [script] reworking cmakefile for swig integration 2022-12-01 12:06:27 -08:00
tangxifan 10d52f1f8b [engine] add swig interface file 2022-12-01 11:54:59 -08:00
tangxifan 74b32c3a5c [script] enable shared library for openfpga 2022-12-01 11:42:25 -08:00
tangxifan f1a317b384 [engine] format 2022-11-24 21:04:04 -08:00
tangxifan 24a174c7a4 [engine] fixed syntax errors 2022-11-23 17:06:27 -08:00
tangxifan 07424b1e7f [engine] now main() is encapuslated in a class OpenfpgaShell 2022-11-23 16:52:22 -08:00
tangxifan c4de6655b6 [engine] bug 2022-10-17 15:26:21 -07:00
tangxifan 0f2b8da7f0 [engine] code format 2022-10-17 14:55:34 -07:00
tangxifan 63d8b00630 [engine] syntax 2022-10-17 14:54:18 -07:00
tangxifan 11624cd0c6 [engine] enabling new feature: pin_table_direction_convention 2022-10-17 14:08:21 -07:00
tangxifan 0af6c76239 [engine] code format 2022-10-13 16:27:57 -07:00
tangxifan d1f3338837 [engine] now repacker find only routable pins when given a net to search routing traces 2022-10-13 16:26:45 -07:00
tangxifan 31da9bf6ea [engine] now repack can find a routing trace from the port in the same type at top-level pb_graph_node 2022-10-13 15:10:25 -07:00
tangxifan afdc071c4c [engine] apply code format 2022-10-06 18:13:33 -07:00
tangxifan e2debd2dde [engine] add missing header files after coding formatter sorts the include files 2022-10-06 18:08:57 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan 0d8d8446ee [test] fixed a bug where OPIN for direct connection is included in GSB 2022-09-30 15:24:51 -07:00
tangxifan fb2693171b [engine] fixed a bug which causes errors in repacker 2022-09-28 16:30:11 -07:00
tangxifan 36b3e64b35 [engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results 2022-09-28 12:17:16 -07:00
tangxifan 3285af4107 [engine] syntax 2022-09-28 11:39:37 -07:00
tangxifan 51f54bbf20 [engine] developing the steps to annotate clustering results 2022-09-27 16:54:48 -07:00
tangxifan 8272d2dcbc [engine] enrich verbose output for repacker, easier to debug 2022-09-27 10:46:57 -07:00
tangxifan e19ca1c6d1 [engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb 2022-09-19 18:49:54 -07:00
tangxifan c922259c23 [engine] remove warnings and update vtr 2022-09-19 14:53:30 -07:00
tangxifan 90ddd2ce32 [engine] now get incoming edges for IPINs only from GSB 2022-09-19 14:02:13 -07:00
tangxifan 3c6ef1925c [engine] now sort ipin incoming edges 2022-09-19 11:00:08 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan f0fe781dbc [engine] fixed a bug 2022-09-16 10:45:27 -07:00
tangxifan bba5b7b070 [engine] syntax 2022-09-15 23:04:37 -07:00
tangxifan cbc71c75c4 [engine] now io indexing follows a natural way 2022-09-15 23:01:35 -07:00
tangxifan 8378ad4bf3 [engine] fixed a bug on mistakenly adding I/O child modules for direct connections 2022-09-14 17:13:23 -07:00
tangxifan 036933dc14 [engine] fixed more bugs due to the extra modules added to top-level module when using memory bank or frame-based protocols 2022-09-14 16:46:10 -07:00
tangxifan 0425b00af5 [engine] fixed a bug for frame-based protocols 2022-09-14 16:41:30 -07:00
tangxifan cb89488f76 [engine] now support a custom list for indexing I/O children in each module 2022-09-14 15:54:55 -07:00
tangxifan eb8b7e6901 [engine] fixed a bug in i/o indexing 2022-09-14 11:30:34 -07:00
tangxifan 1c2192a87d [engine] fixed a few bugs 2022-09-12 16:50:32 -07:00
tangxifan 2fc124e109 [engine] now repack has a new option "--ignore_global_nets_on_pins" 2022-09-12 16:18:26 -07:00
tangxifan e5c7a3df9f [engine] syntax 2022-09-07 15:51:54 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan 8d09773e65 [engine] remove unnecessary checks from sb mirror checker 2022-09-07 11:55:08 +08:00
tangxifan e748c7697d [engine] update code comments 2022-09-06 13:51:29 -07:00
tangxifan eab3580f79 [engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity 2022-09-06 13:40:29 -07:00
tangxifan 59440082ed [engine] fixed some syntax errors 2022-09-06 11:55:40 -07:00
tangxifan 2f84ce5955 [engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used 2022-09-06 11:48:21 -07:00
tangxifan b26b2d0ed0
Merge branch 'master' into vtr_upgrade 2022-09-02 10:05:23 -07:00
coolbreeze413 04abd1a36f add <array> declaration to fix gcc error 2022-09-02 19:26:28 +05:30
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan d3f08a893c [engine] now frame view will not build nets for configuration bus 2022-09-01 20:02:00 -07:00
tangxifan 001367ea41 [engine] syntax 2022-09-01 16:40:17 -07:00
tangxifan 1f5e4d4215 [engine] update fabric bitstream implementation 2022-09-01 16:29:42 -07:00
tangxifan ea6f609181 [engine] fixing a bug in fabric bitstream encoding 2022-09-01 16:28:17 -07:00
tangxifan e4aa6e0ee5 [engine] syntax 2022-09-01 15:17:39 -07:00
tangxifan ee87b5c348 [engine] fixed all the remaining syntax errors due to API mismatches 2022-09-01 09:57:12 -07:00
tangxifan 7c5046cf4e [engine] include the correct header file 2022-09-01 09:23:05 -07:00
tangxifan 71ad0721a1
Merge branch 'master' into vtr_upgrade 2022-08-31 13:56:17 -07:00
tangxifan 26388dfb2f [engine] fixed a bug which causes errors when writing unique GSB to files 2022-08-30 15:45:00 -07:00
tangxifan 3656154913 [engine] fixed syntax errors 2022-08-29 21:17:48 -07:00
tangxifan 2321ea6274 [engine] complete the code required to output rr_gsb with options 2022-08-29 20:44:16 -07:00
tangxifan 12a30196e0 [engine] updating gsb writer; Unfinished!!! 2022-08-29 16:58:48 -07:00
tangxifan b9abdbc5d4 [engine] enable verbose output 2022-08-27 19:59:57 -07:00
tangxifan e9d6e7e38a [engine] update vtr and enable more debugging info 2022-08-27 19:12:43 -07:00
tangxifan 0c2b49ddb9 [engine] remove debugging log output 2022-08-27 13:06:05 -07:00
tangxifan 25f6c529e0 [engine] fixed syntax errors when using clang 2022-08-25 09:58:43 -07:00
tangxifan b432ac05b4 [script] fixed typo on IPO options 2022-08-24 21:51:29 -07:00
tangxifan f853040875 [script] enable IPO in cmakefile 2022-08-24 14:34:33 -07:00
tangxifan ba6ae05091 [engine] update vtr and add in_edge checks to link_arch 2022-08-24 12:22:20 -07:00
tangxifan d1edc51165 [engine] clean up header files that include rr_graph_obj 2022-08-23 18:38:21 -07:00
tangxifan b3e4a06969 [engine] adapt vpr wrapper to the latest main.cpp from vtr 2022-08-23 14:28:05 -07:00
tangxifan 892770a8fb [engine] debugging subtile index failures 2022-08-23 14:13:10 -07:00
tangxifan 0a6b794ef0 [engine] fixed bugs in subtiles. Revisited the usage of client functions 2022-08-23 12:35:04 -07:00
tangxifan 019e663e12 [engine] fixing the bugs on building global nets to sub tile pins 2022-08-23 11:58:44 -07:00
tangxifan 10cefebca8 [engine] fixing bugs on using subtile index 2022-08-23 11:00:23 -07:00
tangxifan ba0ddd01d3 [engine] fixing the bugs on subtiles 2022-08-23 10:52:05 -07:00
tangxifan c17e5d46ab [engine] fixed a bug due to the API of subtile data structure 2022-08-22 21:44:05 -07:00
tangxifan 5d6a90d983 [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
tangxifan 800ce6a290 [engine] avoid function naming conflicts 2022-08-18 19:33:56 -07:00
tangxifan 903dd6cef6 [engine] remove warnings 2022-08-18 15:56:18 -07:00
tangxifan a52597361b [script] remove duplicated libraries in dependency list for some libopenfpga 2022-08-18 11:34:01 -07:00
tangxifan e9c4d102c1 [engine] rename files to avoid conflicts with VPR files 2022-08-17 20:01:50 -07:00
tangxifan 40100c1ba3 [engine] remove warnings 2022-08-17 19:07:49 -07:00
tangxifan cb4b106d4e [engine] correcting syntax errors 2022-08-17 16:36:14 -07:00
tangxifan dfe30df462 [engine] resolve compilation warnings 2022-08-17 16:32:21 -07:00
tangxifan e0ae851e28 [engine] correcting compilation errors due to vpr upgrade 2022-08-17 16:25:12 -07:00
tangxifan ce32c3b30b [engine] fixing api errors 2022-08-17 14:47:14 -07:00
tangxifan 3c2bf5159b [engine] use new API to get node side 2022-08-17 14:38:40 -07:00
tangxifan 3c12810ad9 [engine] debugging 2022-08-17 14:37:13 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 4e871be357 [engine] adapt the use of API in RRGraph for annotation functions 2022-08-17 10:50:16 -07:00
tangxifan 01d53db484 [script] Adapt timing analysis APIs 2022-08-17 10:28:58 -07:00
tangxifan ade8f43a36 [engine] Updating RRGraph Annotation and VTr 2022-08-17 10:16:55 -07:00
tangxifan 716929536d [engine] adapting source files for new APIs in VTR 2022-08-17 09:54:31 -07:00
tangxifan d3d81f0b18 [engine] keep adapting to latest VTR 2022-08-16 21:05:50 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan ce7204daec [engine] debugging 2022-08-16 16:35:08 -07:00
tangxifan c1256ae818 [engine] added command 'pcf2place' to openfpga 2022-07-28 11:30:36 -07:00
tangxifan 2a5bffa6b9 [engine] developing pcf2place integration to openfpga 2022-07-28 10:30:43 -07:00
tangxifan 1c9da96f59 [lib] move io_location_map to libpcf 2022-07-26 16:00:28 -07:00
tangxifan 27fea8bbbe [lib] Merge librepackdc into libpcf 2022-07-26 15:54:32 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 85bcb36f34 [engine] fix compiler errors 2022-07-26 12:25:40 -07:00
tangxifan 0862eceed0 [engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!! 2022-07-26 12:17:45 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan a7e87b9432 [FPGA-Bitstream] note limitations 2022-05-25 18:38:01 +08:00
tangxifan ffac5a66e1 [FPGA-Bitstream] Now encode address bits to save memory in bitstream database 2022-05-25 17:45:08 +08:00
tangxifan bf1a81fbb5 [FPGA-bitstream] add timer to computing intensive functions 2022-05-25 14:52:32 +08:00
tangxifan a20f6eaf06 [Engine] Fixed a few bugs 2022-04-10 21:29:38 +08:00
tangxifan 755be78b39 [Engine] Now GSB output file contains segments name and pin name in SB module 2022-04-10 21:22:30 +08:00
tangxifan 6171abdf95 [FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats 2022-03-29 19:41:15 +08:00
tangxifan 4d67864c2c [Engine] Now global port can be connected partial pins of a tile port 2022-03-20 11:36:03 +08:00
tangxifan 8ab090651a [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
tangxifan 235887e03a [FPGA-Verilog] Fixed a bug on config-enable signals 2022-02-23 22:35:23 -08:00
tangxifan 086642d134 [FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly 2022-02-23 15:33:24 -08:00
tangxifan 1c18d14ad5 [FPGA-Verilog] Add big/little endian support to output ports 2022-02-19 09:23:48 -08:00
tangxifan 3e43a60fdc [FPGA-Verilog] Add big/little endian support when instanciate reference benchmarks 2022-02-19 09:15:38 -08:00
tangxifan 671188dfa4 [FPGA-Verilog] Now support big/little-endian in bus group 2022-02-18 23:05:03 -08:00
tangxifan 790715f46a [FPGA-Verilog] Fixing bugs when using bus group in full testbench generator 2022-02-18 15:41:35 -08:00
tangxifan 401f673f16 [FPGA-Verilog] Streamline codes by using APIs 2022-02-18 14:47:36 -08:00
tangxifan c16ea8d082 [FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches 2022-02-18 14:34:32 -08:00
tangxifan a4dc86a33d [FPGA-Verilog] Now output atom block name removal has a dedicated function 2022-02-18 14:30:46 -08:00
tangxifan f5dd89bbd9 [FPGA-Verilog] Fixed bugs in preconfigured wrapper generator when bus group is used 2022-02-18 14:08:03 -08:00
tangxifan 0d620888ab [FPGA-Verilog] Now instance can output bus ports with all the pins 2022-02-18 12:03:26 -08:00
tangxifan aa375fd7a4 [FPGA-Verilog] Fixed a bug due to the use of bus group in testbench generator 2022-02-18 11:31:11 -08:00
tangxifan 6da0ede9b0 [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan 38601f325b [Engine] Add bus group to OpenFPGA core 2022-02-17 17:28:55 -08:00
tangxifan e67f8ad8b2 [FPGA-Verilog] Now full testbench does not check any output vectors during configuration phase 2022-02-15 17:19:50 -08:00
tangxifan be8f18310d [FPGA-Verilog] Fix a bug on the polarity of reset signals that drive FPGA instances 2022-02-14 17:16:26 -08:00
tangxifan d3f68db228 [FPGA-Verilog] fixing bugs in reset ports for counters in full testbenches 2022-02-14 17:00:54 -08:00
tangxifan 34e192c5ca [FPGA-Verilog] Fixed a bug on wiring FPGA global ports 2022-02-14 15:21:29 -08:00
tangxifan 8d48492ec0 [FPGA-Verilog] Add clock ports to the white list when adding postfix 2022-02-14 11:09:00 -08:00
tangxifan 5794561f7b [FPGA-Verilog] Now shared input wire/register has a postfix in full testbench 2022-02-14 10:39:27 -08:00
tangxifan 2ca73d79e4 [FPGA-Verilog] Fixed the bug on pin constraints 2022-02-13 22:08:06 -08:00
tangxifan b1377f0d34 [FPGA-Verilog] Fix syntax errors 2022-02-13 20:29:05 -08:00
tangxifan 6e132aace4 [FPGA-Verilog] Remove the prefix added by VPR in preconfigured top module 2022-02-13 20:26:21 -08:00
tangxifan fb4106de19 [FPGA-Verilog] Fixed a bug in naming mismatch 2022-02-13 20:06:35 -08:00
tangxifan a068237082 [FPGA-Verilog] Rename internal wire names in testbenches, in order to be consistent with reference benchmarks 2022-02-13 19:55:16 -08:00
tangxifan 1c94d0f285 [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
tangxifan f311a034bb [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
tangxifan 2b8e2de0c9 [FPGA-Verilog] Fix bugs 2022-01-31 14:23:04 -08:00
tangxifan 6c29c286bc [FPGA-Verilog] Fix a bug which cause errors 2022-01-31 14:06:58 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
Emin Cetin 6c2c4e8b14 adding comment 2022-01-28 08:57:45 +03:00
Emin Cetin f9b47c3b34 missing semicolon 2022-01-27 16:49:04 +03:00
Emin Cetin 8f7ee4e338 changing condition of bitstream downloading 2022-01-27 11:49:55 +03:00
tangxifan a9a56686e2 [Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml`` 2022-01-26 11:10:29 -08:00
tangxifan a9e6b7c12e [FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled 2022-01-25 20:33:49 -08:00
tangxifan 33064ca4cf [FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands 2022-01-25 15:51:28 -08:00
tangxifan b09e13b42c [FPGA-Verilog] Fixed a bug on invalid option of a command 2022-01-25 13:45:44 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
nadeemyaseen-rs dbe8616837 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-12-23 00:00:22 +05:00
Tarachand Pagarani 02e4ae9740 allow bitstream setting on hard blocks 2021-12-07 03:42:22 -08:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided 2021-10-30 11:53:46 -07:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00
tangxifan 546350ae41 [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
tangxifan b9c540ec3f [Engine] Upgrade fabric key writer to support BL/WL shift register banks 2021-10-10 21:14:14 -07:00
tangxifan 202b50c0e3 [FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why 2021-10-10 20:57:23 -07:00
tangxifan de3275e9ba [FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains 2021-10-10 16:56:07 -07:00
tangxifan 1c46a92559 [FPGA-Bitstream] Bug fix 2021-10-09 21:59:56 -07:00
tangxifan 6aa4991314 [FPGA-Verilog] Bug fix 2021-10-09 21:34:07 -07:00
tangxifan 7810f376c8 [FPGA-Bitstream] Patch code comments 2021-10-09 21:03:01 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan aac74d9163 [Engine] Bug fix 2021-10-09 18:46:20 -07:00
tangxifan fa08f44107 [Engine] Bug fix 2021-10-09 16:58:56 -07:00
tangxifan 19a551e641 [Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region 2021-10-09 16:44:04 -07:00
tangxifan 932beb480a [Engine] Add fast look-up to the shift register bank data structure 2021-10-08 22:00:01 -07:00
tangxifan e3ff40d9e0 [Engine] Add missing return value 2021-10-08 20:17:55 -07:00
tangxifan 39a69e0d88 [Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols 2021-10-08 17:58:06 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan f7484d4323 [Engine] Update the key memory data structure to contain shift register bank general information 2021-10-08 10:42:18 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan 54a8809b3c [FPGA-Verilog] Bug fix in computing clock frequency for shift register chains 2021-10-06 16:49:28 -07:00
tangxifan 27153bbc89 [FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition 2021-10-06 13:38:51 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 82ed6b177b [FPGA-Verilog] Now consider clock constraints for BL/WL shift registers 2021-10-06 11:39:28 -07:00
tangxifan 2ea9826b17 [FPGA-Bitstream] Bug fix in wrong option name 2021-10-05 18:58:47 -07:00
tangxifan ad54c8547e [FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files 2021-10-05 18:54:02 -07:00
tangxifan fdd75c4ec8 [FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks 2021-10-05 17:54:07 -07:00
tangxifan 3efd6840a8 [Engine] Bug fix for missing WLR ports in auto-generated shift register banks 2021-10-04 16:58:01 -07:00
tangxifan 06b018cfe7 [FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature 2021-10-03 16:05:33 -07:00
tangxifan 2badcb58f2 [FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading 2021-10-03 16:04:47 -07:00
tangxifan 28904ff526 [Engine] Bug fix on wrong port type for shift register chains 2021-10-03 12:31:58 -07:00
tangxifan 756b4c7dc8 [FPGA-Verilog] Bug fix in estimating the simulation period for QuickLogic memory bank using BL/WL shift registers 2021-10-03 12:11:20 -07:00
tangxifan 3eb601531a [FPGA-Verilog] Many bug fixes 2021-10-02 23:39:53 -07:00
tangxifan d453e6477d [FPGA-Verilog] Bug fix 2021-10-02 22:32:57 -07:00
tangxifan 02af633acd [FPGA-Verilog] Fixed several bugs in testbench generator which caused iVerilog errors 2021-10-02 22:14:15 -07:00
tangxifan fa7e168137 [FPGA-Verilog] Now testbench generator connects global shift register clocks to FPGA ports 2021-10-02 22:08:14 -07:00
tangxifan 76d58ebaa0 [FPGA-Verilog] Move clock generator to generic stimuli and shift register clock period is auto tuned by programming clock period 2021-10-02 21:48:10 -07:00
tangxifan 54ec74d8d2 [FPGA-Verilog] Bug fix in code generator 2021-10-02 17:31:37 -07:00