[engine] debugging
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@ -11,7 +11,7 @@
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#include "openfpga_side_manager.h"
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/* Headers from vpr library */
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#include "rr_graph_obj_util.h"
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#include "rr_graph_obj_utils.h"
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#include "openfpga_rr_graph_utils.h"
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#include "annotate_rr_graph.h"
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@ -33,7 +33,7 @@ RRNodeId VprRoutingAnnotation::rr_node_prev_node(const RRNodeId& rr_node) const
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/************************************************************************
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* Public mutators
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***********************************************************************/
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void VprRoutingAnnotation::init(const RRGraph& rr_graph) {
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void VprRoutingAnnotation::init(const RRGraphView& rr_graph) {
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rr_node_nets_.resize(rr_graph.nodes().size(), ClusterNetId::INVALID());
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rr_node_prev_nodes_.resize(rr_graph.nodes().size(), RRNodeId::INVALID());
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}
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@ -7,7 +7,9 @@
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#include <map>
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/* Header from vpr library */
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#include "vpr_context.h"
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#include "vtr_vector.h"
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#include "clustered_netlist_fwd.h"
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#include "rr_graph_view.h"
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/* Begin namespace openfpga */
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namespace openfpga {
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@ -28,7 +30,7 @@ class VprRoutingAnnotation {
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ClusterNetId rr_node_net(const RRNodeId& rr_node) const;
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RRNodeId rr_node_prev_node(const RRNodeId& rr_node) const;
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public: /* Public mutators */
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void init(const RRGraph& rr_graph);
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void init(const RRGraphView& rr_graph);
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void set_rr_node_net(const RRNodeId& rr_node,
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const ClusterNetId& net_id);
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void set_rr_node_prev_node(const RRNodeId& rr_node,
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@ -1 +1,2 @@
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ctags -R . ../../libopenfpga/*/src/* ../../libs/*/src/* ../../vpr/src/*/*
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ctags -R . ../../libopenfpga/*/src/* ../../vtr-verilog-to-routing/libs/*/src/* ../../vtr-verilog-to-routing/libs/*/src/*/* ../../vtr-verilog-to-routing/vpr/src/*/*
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@ -151,7 +151,7 @@
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#include "physical_types.h"
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/* Header from vpr library */
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#include "lb_rr_graph_types.h"
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#include "pack_types.h"
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#include "lb_rr_graph_fwd.h"
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