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[FPGA-Verilog] Fixing bugs in naming wires in verilog testbenches

This commit is contained in:
tangxifan 2022-02-18 14:34:32 -08:00
parent a4dc86a33d
commit c16ea8d082
1 changed files with 9 additions and 0 deletions
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9
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
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@ -706,6 +706,9 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
block_name = remove_atom_block_name_prefix(block_name);
}
/* Bypass clock ports because their stimulus cannot be random */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
@ -741,6 +744,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
block_name = remove_atom_block_name_prefix(block_name);
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);
@ -775,6 +779,9 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
block_name = remove_atom_block_name_prefix(block_name);
}
/* Bypass clock ports because their stimulus cannot be random */
if (clock_port_names.end() != std::find(clock_port_names.begin(), clock_port_names.end(), block_name)) {
@ -897,6 +904,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
block_name = remove_atom_block_name_prefix(block_name);
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + benchmark_output_port_postfix), 1);
@ -919,6 +927,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
block_name = remove_atom_block_name_prefix(block_name);
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + check_flag_port_postfix), 1);