riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[FPGA-Verilog] Now output atom block name removal has a dedicated function

This commit is contained in:
tangxifan 2022-02-18 14:30:46 -08:00
parent f5dd89bbd9
commit a4dc86a33d
6 changed files with 39 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -117,18 +117,11 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp,
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
* VPR added a prefix of "out_" to the output ports of input benchmark
*/
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
std::string(BENCHMARK_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(BENCHMARK_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,
@ -158,19 +151,12 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
print_verilog_comment(fp, std::string("----- FPGA fabric instanciation -------"));
/* VPR added a prefix of "out_" to the output ports of input benchmark */
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
/* Always use explicit port mapping */
print_verilog_testbench_benchmark_instance(fp, std::string(circuit_name + std::string(FORMAL_VERIFICATION_TOP_MODULE_POSTFIX)),
std::string(FPGA_INSTANCE_NAME),
std::string(),
std::string(),
std::string(),
prefix_to_remove,
std::string(FPGA_PORT_POSTFIX),
std::vector<std::string>(),
atom_ctx, netlist_annotation,

29
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -22,6 +22,7 @@
#include "module_manager_utils.h"
#include "fabric_global_port_info_utils.h"
#include "openfpga_atom_netlist_utils.h"
#include "verilog_constants.h"
#include "verilog_writer_utils.h"
@ -79,7 +80,6 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,
@ -109,6 +109,13 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
block_name = netlist_annotation.block_name(atom_blk);
}
/* Note that VPR added a prefix "out_" or "out:" to the name of output blocks
* We can remove this when specified through input argument
*/
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
block_name = remove_atom_block_name_prefix(block_name);
}
/* If the pin is part of a bus,
* - Check if the bus is already in the list
* - If not, add it to the port list
@ -195,21 +202,8 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
}
} else {
VTR_ASSERT_SAFE(AtomBlockType::OUTPAD == port_types[iport]);
/* Note that VPR added a prefix "out_" or "out:" to the name of output blocks
* We can remove this when specified through input argument
*/
std::string output_block_name = port_names[iport];
for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
if (!prefix_to_remove.empty()) {
if (0 == output_block_name.find(prefix_to_remove)) {
output_block_name.erase(0, prefix_to_remove.length());
break;
}
}
}
if (true == use_explicit_port_map) {
fp << "." << output_block_name << module_output_port_postfix << "(";
fp << "." << port_names[iport] << module_output_port_postfix << "(";
}
/* For bus ports, include a complete list of pins */
@ -237,7 +231,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
/* Update the counter */
port_counter++;
}
fp << "\t);" << std::endl;
fp << "\n\t);" << std::endl;
}
/********************************************************************
@ -576,6 +570,7 @@ void print_verilog_testbench_check(std::fstream& fp,
}
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
block_name = remove_atom_block_name_prefix(block_name);
fp << "\t\t\tif(!(" << block_name << fpga_port_postfix;
fp << " === " << block_name << benchmark_port_postfix;
fp << ") && !(" << block_name << benchmark_port_postfix;
@ -603,6 +598,7 @@ void print_verilog_testbench_check(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
block_name = remove_atom_block_name_prefix(block_name);
fp << "\talways@(posedge " << block_name << check_flag_port_postfix << ") begin" << std::endl;
fp << "\t\tif(" << block_name << check_flag_port_postfix << ") begin" << std::endl;
@ -874,6 +870,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp,
if (true == netlist_annotation.is_block_renamed(atom_blk)) {
block_name = netlist_annotation.block_name(atom_blk);
}
block_name = remove_atom_block_name_prefix(block_name);
/* Each logical block assumes a single-width port */
BasicPort output_port(std::string(block_name + fpga_output_port_postfix), 1);

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -39,7 +39,6 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp,
const std::string& module_input_port_postfix,
const std::string& module_output_port_postfix,
const std::string& input_port_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::string& output_port_postfix,
const std::vector<std::string>& clock_port_names,
const AtomContext& atom_ctx,

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -946,18 +946,11 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp,
/* Instanciate benchmark */
print_verilog_comment(fp, std::string("----- Reference Benchmark Instanication -------"));
/* Do NOT use explicit port mapping here:
* VPR added a prefix of "out_" to the output ports of input benchmark
*/
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
print_verilog_testbench_benchmark_instance(fp, reference_verilog_top_name,
std::string(TOP_TESTBENCH_REFERENCE_INSTANCE_NAME),
std::string(),
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
prefix_to_remove,
std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX),
clock_port_names,
atom_ctx, netlist_annotation,

24
openfpga/src/utils/openfpga_atom_netlist_utils.cpp
View File

@ -11,6 +11,7 @@
/* Headers from vtrutil library */
#include "atom_netlist_utils.h"
#include "openfpga_reserved_words.h"
#include "openfpga_atom_netlist_utils.h"
/* begin namespace openfpga */
@ -38,4 +39,27 @@ std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& a
return clock_names;
}
/********************************************************************
* Remove the prefix that is added to the name of a output block (by VPR)
*******************************************************************/
std::string remove_atom_block_name_prefix(const std::string& block_name) {
/* VPR added a prefix of "out_" to the output ports of input benchmark */
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
std::string ret_block_name = block_name;
for (const std::string& cur_prefix_to_remove : prefix_to_remove) {
if (!cur_prefix_to_remove.empty()) {
if (0 == ret_block_name.find(cur_prefix_to_remove)) {
ret_block_name.erase(0, cur_prefix_to_remove.length());
break;
}
}
}
return ret_block_name;
}
} /* end namespace openfpga */

2
openfpga/src/utils/openfpga_atom_netlist_utils.h
View File

@ -19,6 +19,8 @@ namespace openfpga {
std::vector<std::string> find_atom_netlist_clock_port_names(const AtomNetlist& atom_nlist,
const VprNetlistAnnotation& netlist_annotation);
std::string remove_atom_block_name_prefix(const std::string& block_name);
} /* end namespace openfpga */
#endif