[engine] add standalone vpr commands
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@ -18,9 +18,19 @@ void add_vpr_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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ShellCommandId shell_cmd_vpr_id =
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shell.add_command(shell_cmd_vpr,
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"Start VPR core engine to pack, place and route a BLIF "
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"design on a FPGA architecture");
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"design on a FPGA architecture; Note that this command will keep VPR results!");
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shell.set_command_class(shell_cmd_vpr_id, vpr_cmd_class);
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shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr);
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shell.set_command_execute_function(shell_cmd_vpr_id, vpr::vpr_wrapper);
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/* Create a macro command of 'vpr_standalone' which will call the main engine of vpr in a standalone way
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*/
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Command shell_cmd_vpr_stdalone("vpr_standalone");
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ShellCommandId shell_cmd_vpr_stdalone_id =
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shell.add_command(shell_cmd_vpr,
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"Start a standalone VPR core engine to pack, place and route a BLIF "
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"design on a FPGA architecture; Note that this command will NOT keep VPR results!");
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shell.set_command_class(shell_cmd_vpr_stdalone_id, vpr_cmd_class);
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shell.set_command_execute_function(shell_cmd_vpr_stdalone_id, vpr::vpr_standalone_wrapper);
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}
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} /* end namespace openfpga */
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@ -19,10 +19,12 @@
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#include "vtr_log.h"
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#include "vtr_memory.h"
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#include "vtr_time.h"
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#include "command_exit_codes.h"
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namespace vpr {
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/**
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* VPR program without clean up
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* VPR program
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* Generate FPGA architecture given architecture description
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* Pack, place, and route circuit into FPGA architecture
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@ -34,6 +36,7 @@ namespace vpr {
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* 3. Place-and-route and timing analysis
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* 4. Clean up
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*/
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static
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int vpr(int argc, char** argv) {
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vtr::ScopedFinishTimer t("The entire flow of VPR");
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@ -93,4 +96,86 @@ int vpr(int argc, char** argv) {
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return SUCCESS_EXIT_CODE;
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}
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/* A wrapper to return proper codes for openfpga shell */
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int vpr_wrapper(int argc, char** argv) {
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if (SUCCESS_EXIT_CODE != vpr(argc, argv)) {
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return openfpga::CMD_EXEC_FATAL_ERROR;
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}
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return openfpga::CMD_EXEC_SUCCESS;
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}
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/**
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* VPR program with clean up
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*/
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static
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int vpr_standalone(int argc, char** argv) {
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vtr::ScopedFinishTimer t("The entire flow of VPR");
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t_options Options = t_options();
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t_arch Arch = t_arch();
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t_vpr_setup vpr_setup = t_vpr_setup();
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try {
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vpr_install_signal_handler();
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/* Read options, architecture, and circuit netlist */
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vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, &Arch);
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if (Options.show_version) {
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vpr_free_all(Arch, vpr_setup);
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return SUCCESS_EXIT_CODE;
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}
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bool flow_succeeded = vpr_flow(vpr_setup, Arch);
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if (!flow_succeeded) {
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VTR_LOG("VPR failed to implement circuit\n");
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vpr_free_all(Arch, vpr_setup);
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return UNIMPLEMENTABLE_EXIT_CODE;
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}
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auto& timing_ctx = g_vpr_ctx.timing();
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print_timing_stats("Flow", timing_ctx.stats);
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/* free data structures */
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vpr_free_all(Arch, vpr_setup);
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VTR_LOG("VPR succeeded\n");
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} catch (const tatum::Error& tatum_error) {
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VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str());
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vpr_free_all(Arch, vpr_setup);
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return ERROR_EXIT_CODE;
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} catch (const VprError& vpr_error) {
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vpr_print_error(vpr_error);
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if (vpr_error.type() == VPR_ERROR_INTERRUPTED) {
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vpr_free_all(Arch, vpr_setup);
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return INTERRUPTED_EXIT_CODE;
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} else {
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vpr_free_all(Arch, vpr_setup);
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return ERROR_EXIT_CODE;
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}
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} catch (const vtr::VtrError& vtr_error) {
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VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(), vtr_error.what());
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vpr_free_all(Arch, vpr_setup);
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return ERROR_EXIT_CODE;
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}
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/* Signal success to scripts */
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return SUCCESS_EXIT_CODE;
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}
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/* A wrapper to return proper codes for openfpga shell */
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int vpr_standalone_wrapper(int argc, char** argv) {
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if (SUCCESS_EXIT_CODE != vpr_standalone(argc, argv)) {
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return openfpga::CMD_EXEC_FATAL_ERROR;
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}
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return openfpga::CMD_EXEC_SUCCESS;
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}
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} /* End namespace vpr */
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@ -4,7 +4,9 @@
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/* Begin namespace vpr */
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namespace vpr {
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int vpr(int argc, char** argv);
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int vpr_wrapper(int argc, char** argv);
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int vpr_standalone_wrapper(int argc, char** argv);
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} /* End namespace vpr */
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