[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
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@ -29,14 +29,13 @@ bool annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
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}
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auto logical_block = clustering_ctx.clb_nlist.block_type(cluster_blk_id);
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for (int ipin = 0; ipin < logical_block->pb_type->num_pins; ++ipin) {
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ClusterNetId pre_routing_net_id = clustering_ctx.clb_nlist.block_net(cluster_blk_id, ipin);
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ClusterNetId post_routing_net_id = ClusterNetId::INVALID();
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auto search_result = clustering_ctx.post_routing_clb_pin_nets.at(cluster_blk_id).find(ipin);
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if (search_result != clustering_ctx.post_routing_clb_pin_nets.at(cluster_blk_id).end()) {
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post_routing_net_id = search_result->second;
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}
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if (post_routing_net_id) {
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clustering_annotation.rename_net(cluster_blk_id, ipin, post_routing_net_id);
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/* Update pin remapping from vtr data storage */
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auto blk_search_result = clustering_ctx.post_routing_clb_pin_nets.find(cluster_blk_id);
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if (blk_search_result != clustering_ctx.post_routing_clb_pin_nets.end()) {
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auto pin_search_result = blk_search_result->second.find(ipin);
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if (pin_search_result != blk_search_result->second.end()) {
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clustering_annotation.rename_net(cluster_blk_id, ipin, pin_search_result->second);
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}
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}
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}
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}
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@ -92,4 +92,8 @@ PhysicalPb& VprClusteringAnnotation::mutable_physical_pb(const ClusterBlockId& b
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return physical_pbs_.at(block_id);
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}
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void VprClusteringAnnotation::clear_net_remapping() {
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net_names_.clear();
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}
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} /* End namespace openfpga*/
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@ -42,6 +42,8 @@ class VprClusteringAnnotation {
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void adapt_truth_table(t_pb* pb, const AtomNetlist::TruthTable& tt);
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void add_physical_pb(const ClusterBlockId& block_id, const PhysicalPb& physical_pb);
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PhysicalPb& mutable_physical_pb(const ClusterBlockId& block_id);
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public: /* Clean-up */
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void clear_net_remapping();
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private: /* Internal data */
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/* Pair a regular pb_type to its physical pb_type */
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std::map<ClusterBlockId, std::map<int, ClusterNetId>> net_names_;
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@ -93,8 +93,19 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
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/* Get the cluster net id which has been mapped to this net */
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ClusterNetId routing_net_id = vpr_routing_annotation.rr_node_net(rr_node);
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/* Find the net mapped to this pin in clustering results*/
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/* Find the net mapped to this pin in clustering results. There are two sources:
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* - The original clustering netlist, where the pin mapping is based on pre-routing
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* - The post-routing pin mapping, where the pin mapping is based on post-routing
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* We always check the original clustering netlist first, if there is any remapping, check the remapping data
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*/
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ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(blk_id, j);
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auto blk_search_result = clustering_ctx.post_routing_clb_pin_nets.find(blk_id);
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if (blk_search_result != clustering_ctx.post_routing_clb_pin_nets.end()) {
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auto pin_search_result = blk_search_result->second.find(j);
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if (pin_search_result != blk_search_result->second.end()) {
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cluster_net_id = pin_search_result->second;
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}
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}
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/* Ignore those net have never been routed: this check is valid only
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* when both packer has mapped a net to the pin and the router leaves the pin to be unmapped
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@ -181,6 +192,9 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
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const VprRoutingAnnotation& vpr_routing_annotation,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const bool& verbose) {
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/* Ensure a clean start: remove all the remapping results from VTR's post-routing clustering result sync-up */
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vpr_clustering_annotation.clear_net_remapping();
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/* Update the core logic (center blocks of the FPGA) */
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for (size_t x = 1; x < device_ctx.grid.width() - 1; ++x) {
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for (size_t y = 1; y < device_ctx.grid.height() - 1; ++y) {
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