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[FPGA-Verilog] Streamline codes by using APIs

This commit is contained in:
tangxifan 2022-02-18 14:47:36 -08:00
parent c16ea8d082
commit 401f673f16
4 changed files with 2 additions and 15 deletions
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4
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -517,9 +517,6 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
}
/* Connect I/Os to benchmark I/Os or constant driver */
std::vector<std::string> prefix_to_remove;
prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
@ -527,7 +524,6 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
std::string(),
std::string(),
prefix_to_remove,
std::vector<std::string>(),
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);

11
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -252,7 +252,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& net_name_postfix,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value) {
/* Validate the file stream */
@ -348,16 +347,10 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
/* Note that VPR added a prefix to the name of output blocks
* We can remove this when specified through input argument
*/
for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
if (!prefix_to_remove.empty()) {
if (0 == block_name.find(prefix_to_remove)) {
block_name.erase(0, prefix_to_remove.length());
break;
}
}
if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
block_name = remove_atom_block_name_prefix(block_name);
}
/* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1
* In addition, the input and output ports may have different postfix in naming
* due to verification context! Here, we give full customization on naming

1
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -58,7 +58,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
const std::string& net_name_postfix,
const std::string& io_input_port_name_postfix,
const std::string& io_output_port_name_postfix,
const std::vector<std::string>& output_port_prefix_to_remove,
const std::vector<std::string>& clock_port_names,
const size_t& unused_io_value);

1
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2064,7 +2064,6 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
std::string(),
std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
std::vector<std::string>(),
clock_port_names,
(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);