[FPGA-Verilog] Streamline codes by using APIs
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c16ea8d082
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@ -517,9 +517,6 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
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}
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/* Connect I/Os to benchmark I/Os or constant driver */
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std::vector<std::string> prefix_to_remove;
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prefix_to_remove.push_back(std::string(VPR_BENCHMARK_OUT_PORT_PREFIX));
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prefix_to_remove.push_back(std::string(OPENFPGA_BENCHMARK_OUT_PORT_PREFIX));
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print_verilog_testbench_connect_fpga_ios(fp, module_manager, top_module,
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atom_ctx, place_ctx, io_location_map,
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netlist_annotation,
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@ -527,7 +524,6 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
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std::string(FORMAL_VERIFICATION_TOP_MODULE_PORT_POSTFIX),
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std::string(),
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std::string(),
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prefix_to_remove,
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std::vector<std::string>(),
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(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
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@ -252,7 +252,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
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const std::string& net_name_postfix,
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const std::string& io_input_port_name_postfix,
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const std::string& io_output_port_name_postfix,
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const std::vector<std::string>& output_port_prefix_to_remove,
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const std::vector<std::string>& clock_port_names,
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const size_t& unused_io_value) {
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/* Validate the file stream */
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@ -348,16 +347,10 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
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/* Note that VPR added a prefix to the name of output blocks
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* We can remove this when specified through input argument
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*/
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for (const std::string& prefix_to_remove : output_port_prefix_to_remove) {
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if (!prefix_to_remove.empty()) {
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if (0 == block_name.find(prefix_to_remove)) {
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block_name.erase(0, prefix_to_remove.length());
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break;
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}
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}
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if (AtomBlockType::OUTPAD == atom_ctx.nlist.block_type(atom_blk)) {
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block_name = remove_atom_block_name_prefix(block_name);
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}
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/* Create the port for benchmark I/O, due to BLIF benchmark, each I/O always has a size of 1
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* In addition, the input and output ports may have different postfix in naming
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* due to verification context! Here, we give full customization on naming
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@ -58,7 +58,6 @@ void print_verilog_testbench_connect_fpga_ios(std::fstream& fp,
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const std::string& net_name_postfix,
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const std::string& io_input_port_name_postfix,
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const std::string& io_output_port_name_postfix,
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const std::vector<std::string>& output_port_prefix_to_remove,
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const std::vector<std::string>& clock_port_names,
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const size_t& unused_io_value);
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@ -2064,7 +2064,6 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
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std::string(),
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std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX),
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std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX),
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std::vector<std::string>(),
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clock_port_names,
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(size_t)VERILOG_DEFAULT_SIGNAL_INIT_VALUE);
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