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[engine] correcting syntax errors

This commit is contained in:
tangxifan 2022-08-17 16:36:14 -07:00
parent dfe30df462
commit cb4b106d4e
2 changed files with 2 additions and 2 deletions
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2
openfpga/src/tile_direct/build_tile_direct.cpp
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@ -90,7 +90,7 @@ std::vector<size_t> find_physical_tile_pin_id(t_physical_tile_type_ptr physical_
std::vector<size_t> pin_ids;
/* Walk through the port of the tile */
for (const t_sub_tile& sub_tile : physical_tile.sub_tiles) {
for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
for (const t_physical_tile_port& physical_tile_port : sub_tile.ports) {
if (std::string(physical_tile_port.name) != tile_port.get_name()) {
continue;

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 090322cd55f02e6f2d359e58afd91c3e486bfba9
Subproject commit a18c4199afb5a4350c171d3e8be7116330d2a67b