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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface

This commit is contained in:
tangxifan 2021-10-08 15:25:37 -07:00
parent f7484d4323
commit 8f5f30792f
19 changed files with 370 additions and 130 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
openfpga/src/base/openfpga_context.h
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@ -66,7 +66,7 @@ class OpenfpgaContext : public Context {
const openfpga::DeviceRRGSB& device_rr_gsb() const { return device_rr_gsb_; }
const openfpga::MuxLibrary& mux_lib() const { return mux_lib_; }
const openfpga::DecoderLibrary& decoder_lib() const { return decoder_lib_; }
const std::array<openfpga::MemoryBankShiftRegisterBanks, 2>& blwl_shift_register_banks() { return blwl_sr_banks_; }
const openfpga::MemoryBankShiftRegisterBanks& blwl_shift_register_banks() { return blwl_sr_banks_; }
const openfpga::TileDirect& tile_direct() const { return tile_direct_; }
const openfpga::ModuleManager& module_graph() const { return module_graph_; }
const openfpga::FlowManager& flow_manager() const { return flow_manager_; }
@ -89,7 +89,7 @@ class OpenfpgaContext : public Context {
openfpga::DeviceRRGSB& mutable_device_rr_gsb() { return device_rr_gsb_; }
openfpga::MuxLibrary& mutable_mux_lib() { return mux_lib_; }
openfpga::DecoderLibrary& mutable_decoder_lib() { return decoder_lib_; }
std::array<openfpga::MemoryBankShiftRegisterBanks, 2>& mutable_blwl_shift_register_banks() { return blwl_sr_banks_; }
openfpga::MemoryBankShiftRegisterBanks& mutable_blwl_shift_register_banks() { return blwl_sr_banks_; }
openfpga::TileDirect& mutable_tile_direct() { return tile_direct_; }
openfpga::ModuleManager& mutable_module_graph() { return module_graph_; }
openfpga::FlowManager& mutable_flow_manager() { return flow_manager_; }
@ -138,7 +138,7 @@ class OpenfpgaContext : public Context {
/* Library of shift register banks that control BLs and WLs
* @note Only used when memory bank is used as configuration protocol
*/
std::array<openfpga::MemoryBankShiftRegisterBanks, 2> blwl_sr_banks_;
openfpga::MemoryBankShiftRegisterBanks blwl_sr_banks_;
/* Fabric module graph */
openfpga::ModuleManager module_graph_;

2
openfpga/src/fabric/build_device_module.cpp
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@ -31,7 +31,7 @@ namespace openfpga {
*******************************************************************/
int build_device_module_graph(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const OpenfpgaContext& openfpga_ctx,
const DeviceContext& vpr_device_ctx,
const bool& frame_view,

2
openfpga/src/fabric/build_device_module.h
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@ -17,7 +17,7 @@ namespace openfpga {
int build_device_module_graph(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const OpenfpgaContext& openfpga_ctx,
const DeviceContext& vpr_device_ctx,
const bool& frame_view,

2
openfpga/src/fabric/build_top_module.cpp
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@ -283,7 +283,7 @@ vtr::Matrix<size_t> add_top_module_connection_block_instances(ModuleManager& mod
*******************************************************************/
int build_top_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,

2
openfpga/src/fabric/build_top_module.h
View File

@ -30,7 +30,7 @@ namespace openfpga {
int build_top_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary& circuit_lib,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceGrid& grids,

4
openfpga/src/fabric/build_top_module_memory.cpp
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@ -1735,7 +1735,7 @@ void add_top_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_mana
static
void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ModuleId& parent_module,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol,
@ -1802,7 +1802,7 @@ void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
*******************************************************************/
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ModuleId& parent_module,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol,

2
openfpga/src/fabric/build_top_module_memory.h
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@ -65,7 +65,7 @@ void add_top_module_sram_ports(ModuleManager& module_manager,
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ModuleId& parent_module,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol,

119
openfpga/src/fabric/build_top_module_memory_bank.cpp
View File

@ -1086,9 +1086,25 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_heads(ModuleMan
ModulePortId blsr_head_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(head_port_name, config_region));
BasicPort blsr_head_port_info = module_manager.module_port(top_module, blsr_head_port);
for (size_t iinst = 0; iinst < sr_banks.shift_register_bank_modules(config_region).size(); ++iinst) {
ModuleId sr_bank_module = sr_banks.shift_register_bank_modules(config_region)[iinst];
size_t sr_bank_instance = sr_banks.shift_register_bank_instances(config_region)[iinst];
size_t num_sr_bank_modules;
if (std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME) == head_port_name) {
num_sr_bank_modules = sr_banks.bl_shift_register_bank_modules(config_region).size();
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME) == head_port_name);
num_sr_bank_modules = sr_banks.wl_shift_register_bank_modules(config_region).size();
}
for (size_t iinst = 0; iinst < num_sr_bank_modules; ++iinst) {
ModuleId sr_bank_module;
size_t sr_bank_instance;
if (std::string(BL_SHIFT_REGISTER_CHAIN_HEAD_NAME) == head_port_name) {
sr_bank_module = sr_banks.bl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.bl_shift_register_bank_instances(config_region)[iinst];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_HEAD_NAME) == head_port_name);
sr_bank_module = sr_banks.wl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.wl_shift_register_bank_instances(config_region)[iinst];
}
VTR_ASSERT(sr_bank_module);
ModulePortId sr_module_head_port = module_manager.find_module_port(sr_bank_module, head_port_name);
@ -1125,10 +1141,24 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_tails(ModuleMan
ModulePortId blsr_tail_port = module_manager.find_module_port(top_module, generate_regional_blwl_port_name(tail_port_name, config_region));
BasicPort blsr_tail_port_info = module_manager.module_port(top_module, blsr_tail_port);
for (size_t iinst = 0; iinst < sr_banks.shift_register_bank_modules(config_region).size(); ++iinst) {
ModuleId sr_bank_module = sr_banks.shift_register_bank_modules(config_region)[iinst];
size_t sr_bank_instance = sr_banks.shift_register_bank_instances(config_region)[iinst];
VTR_ASSERT(sr_bank_module);
size_t num_sr_bank_modules;
if (std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME) == tail_port_name) {
num_sr_bank_modules = sr_banks.bl_shift_register_bank_modules(config_region).size();
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME) == tail_port_name);
num_sr_bank_modules = sr_banks.wl_shift_register_bank_modules(config_region).size();
}
for (size_t iinst = 0; iinst < num_sr_bank_modules; ++iinst) {
ModuleId sr_bank_module;
size_t sr_bank_instance;
if (std::string(BL_SHIFT_REGISTER_CHAIN_TAIL_NAME) == tail_port_name) {
sr_bank_module = sr_banks.bl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.bl_shift_register_bank_instances(config_region)[iinst];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_TAIL_NAME) == tail_port_name);
sr_bank_module = sr_banks.wl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.wl_shift_register_bank_instances(config_region)[iinst];
}
ModulePortId sr_module_tail_port = module_manager.find_module_port(sr_bank_module, tail_port_name);
BasicPort sr_module_tail_port_info = module_manager.module_port(sr_bank_module, sr_module_tail_port);
@ -1183,9 +1213,25 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
const std::string& child_blwl_port_name,
const bool& optional_blwl = false) {
for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
for (size_t iinst = 0; iinst < sr_banks.shift_register_bank_modules(config_region).size(); ++iinst) {
ModuleId sr_bank_module = sr_banks.shift_register_bank_modules(config_region)[iinst];
size_t sr_bank_instance = sr_banks.shift_register_bank_instances(config_region)[iinst];
size_t num_sr_bank_modules;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
num_sr_bank_modules = sr_banks.bl_shift_register_bank_modules(config_region).size();
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
num_sr_bank_modules = sr_banks.wl_shift_register_bank_modules(config_region).size();
}
for (size_t iinst = 0; iinst < num_sr_bank_modules; ++iinst) {
ModuleId sr_bank_module;
size_t sr_bank_instance;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
sr_bank_module = sr_banks.bl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.bl_shift_register_bank_instances(config_region)[iinst];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
sr_bank_module = sr_banks.wl_shift_register_bank_modules(config_region)[iinst];
sr_bank_instance = sr_banks.wl_shift_register_bank_instances(config_region)[iinst];
}
VTR_ASSERT(sr_bank_module);
ModulePortId sr_module_blwl_port = module_manager.find_module_port(sr_bank_module, sr_blwl_port_name);
@ -1195,9 +1241,23 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
VTR_ASSERT(sr_module_blwl_port);
BasicPort sr_module_blwl_port_info = module_manager.module_port(sr_bank_module, sr_module_blwl_port);
size_t num_sink_child_ids;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
num_sink_child_ids = sr_banks.bl_shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance).size();
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
num_sink_child_ids = sr_banks.wl_shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance).size();
}
for (size_t sink_id = 0; sink_id < num_sink_child_ids; ++sink_id) {
size_t child_id;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
child_id = sr_banks.bl_shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
child_id = sr_banks.wl_shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
}
for (size_t sink_id = 0; sink_id < sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance).size(); ++sink_id) {
size_t child_id = sr_banks.shift_register_bank_sink_child_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
ModuleId child_module = module_manager.region_configurable_children(top_module, config_region)[child_id];
size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[child_id];
@ -1205,7 +1265,13 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
ModulePortId child_blwl_port = module_manager.find_module_port(child_module, child_blwl_port_name);
BasicPort child_blwl_port_info = module_manager.module_port(child_module, child_blwl_port);
size_t cur_sr_module_blwl_pin_id = sr_banks.shift_register_bank_source_blwl_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
size_t cur_sr_module_blwl_pin_id;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
cur_sr_module_blwl_pin_id = sr_banks.bl_shift_register_bank_source_blwl_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
cur_sr_module_blwl_pin_id = sr_banks.wl_shift_register_bank_source_blwl_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
}
/* Create net */
ModuleNetId net = create_module_source_pin_net(module_manager, top_module,
@ -1215,7 +1281,14 @@ void add_top_module_nets_cmos_ql_memory_bank_shift_register_bank_blwls(ModuleMan
VTR_ASSERT(ModuleNetId::INVALID() != net);
/* Add net sink */
size_t sink_pin_id = sr_banks.shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
size_t sink_pin_id;
if (std::string(BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME) == sr_blwl_port_name) {
sink_pin_id = sr_banks.bl_shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
} else {
VTR_ASSERT(std::string(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME) == sr_blwl_port_name);
sink_pin_id = sr_banks.wl_shift_register_bank_sink_pin_ids(config_region, sr_bank_module, sr_bank_instance)[sink_id];
}
module_manager.add_module_net_sink(top_module, net,
child_module, child_instance, child_blwl_port, sink_pin_id);
}
@ -1315,7 +1388,7 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module);
module_manager.add_child_module(top_module, sr_bank_module);
sr_banks.add_shift_register_instance(config_region, sr_bank_module, cur_inst);
sr_banks.add_bl_shift_register_instance(config_region, sr_bank_module, cur_inst);
/**************************************************************
* Precompute the BLs and WLs distribution across the FPGA fabric
@ -1340,8 +1413,8 @@ void add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(Module
for (const size_t& sink_bl_pin : child_bl_port_info.pins()) {
size_t bl_pin_id = bl_start_index_per_tile[coord.x()] + cur_bl_index;
sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_bl_pin);
sr_banks.add_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, bl_pin_id);
sr_banks.add_bl_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_bl_pin);
sr_banks.add_bl_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, bl_pin_id);
cur_bl_index++;
}
@ -1409,7 +1482,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
size_t cur_inst = module_manager.num_instance(top_module, sr_bank_module);
module_manager.add_child_module(top_module, sr_bank_module);
sr_banks.add_shift_register_instance(config_region, sr_bank_module, cur_inst);
sr_banks.add_wl_shift_register_instance(config_region, sr_bank_module, cur_inst);
/**************************************************************
* Precompute the BLs and WLs distribution across the FPGA fabric
@ -1433,8 +1506,8 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
for (const size_t& sink_wl_pin : child_wl_port_info.pins()) {
size_t wl_pin_id = wl_start_index_per_tile[coord.y()] + cur_wl_index;
sr_banks.add_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_wl_pin);
sr_banks.add_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, wl_pin_id);
sr_banks.add_wl_shift_register_sink_nodes(config_region, sr_bank_module, cur_inst, child_id, sink_wl_pin);
sr_banks.add_wl_shift_register_source_blwls(config_region, sr_bank_module, cur_inst, wl_pin_id);
cur_wl_index++;
}
@ -1477,7 +1550,7 @@ void add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(Module
********************************************************************/
void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol,
@ -1495,7 +1568,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
break;
}
case BLWL_PROTOCOL_SHIFT_REGISTER: {
add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(module_manager, blwl_sr_banks[0], top_module, circuit_lib, config_protocol);
add_top_module_nets_cmos_ql_memory_bank_bl_shift_register_config_bus(module_manager, blwl_sr_banks, top_module, circuit_lib, config_protocol);
break;
}
default: {
@ -1514,7 +1587,7 @@ void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_ma
break;
}
case BLWL_PROTOCOL_SHIFT_REGISTER: {
add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(module_manager, blwl_sr_banks[1], top_module, circuit_lib, config_protocol);
add_top_module_nets_cmos_ql_memory_bank_wl_shift_register_config_bus(module_manager, blwl_sr_banks, top_module, circuit_lib, config_protocol);
break;
}
default: {

2
openfpga/src/fabric/build_top_module_memory_bank.h
View File

@ -26,7 +26,7 @@ namespace openfpga {
void add_top_module_nets_cmos_ql_memory_bank_config_bus(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ModuleId& top_module,
const CircuitLibrary& circuit_lib,
const ConfigProtocol& config_protocol,

186
openfpga/src/fabric/memory_bank_shift_register_banks.cpp
View File

@ -53,9 +53,9 @@ FabricKey::fabric_word_line_bank_range MemoryBankShiftRegisterBanks::wl_banks(co
return vtr::make_range(wl_bank_ids_[region_id].begin(), wl_bank_ids_[region_id].end());
}
std::vector<ModuleId> MemoryBankShiftRegisterBanks::shift_register_bank_unique_modules() const {
std::vector<ModuleId> MemoryBankShiftRegisterBanks::bl_shift_register_bank_unique_modules() const {
std::vector<ModuleId> sr_bank_modules;
for (const auto& region : sr_instance_sink_child_ids_) {
for (const auto& region : bl_sr_instance_sink_child_ids_) {
for (const auto& pair : region) {
if (sr_bank_modules.end() == std::find(sr_bank_modules.begin(), sr_bank_modules.end(), pair.first.first)) {
sr_bank_modules.push_back(pair.first.first);
@ -65,58 +65,127 @@ std::vector<ModuleId> MemoryBankShiftRegisterBanks::shift_register_bank_unique_m
return sr_bank_modules;
}
std::vector<ModuleId> MemoryBankShiftRegisterBanks::shift_register_bank_modules(const ConfigRegionId& region) const {
std::vector<ModuleId> MemoryBankShiftRegisterBanks::bl_shift_register_bank_modules(const ConfigRegionId& region) const {
std::vector<ModuleId> sr_bank_modules;
VTR_ASSERT(valid_region_id(region));
for (const auto& pair : sr_instance_sink_child_ids_[region]) {
for (const auto& pair : bl_sr_instance_sink_child_ids_[region]) {
sr_bank_modules.push_back(pair.first.first);
}
return sr_bank_modules;
}
std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_instances(const ConfigRegionId& region) const {
std::vector<size_t> MemoryBankShiftRegisterBanks::bl_shift_register_bank_instances(const ConfigRegionId& region) const {
std::vector<size_t> sr_bank_instances;
VTR_ASSERT(valid_region_id(region));
for (const auto& pair : sr_instance_sink_child_ids_[region]) {
for (const auto& pair : bl_sr_instance_sink_child_ids_[region]) {
sr_bank_instances.push_back(pair.first.second);
}
return sr_bank_instances;
}
std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
std::vector<size_t> MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = sr_instance_sink_child_ids_[region].find(std::make_pair(sr_module, sr_instance));
auto result = bl_sr_instance_sink_child_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != sr_instance_sink_child_ids_[region].end()) {
if (result != bl_sr_instance_sink_child_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
std::vector<size_t> MemoryBankShiftRegisterBanks::bl_shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = sr_instance_sink_child_pin_ids_[region].find(std::make_pair(sr_module, sr_instance));
auto result = bl_sr_instance_sink_child_pin_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != sr_instance_sink_child_pin_ids_[region].end()) {
if (result != bl_sr_instance_sink_child_pin_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
std::vector<size_t> MemoryBankShiftRegisterBanks::shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
std::vector<size_t> MemoryBankShiftRegisterBanks::bl_shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = bl_sr_instance_source_blwl_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != bl_sr_instance_source_blwl_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
std::vector<ModuleId> MemoryBankShiftRegisterBanks::wl_shift_register_bank_unique_modules() const {
std::vector<ModuleId> sr_bank_modules;
for (const auto& region : wl_sr_instance_sink_child_ids_) {
for (const auto& pair : region) {
if (sr_bank_modules.end() == std::find(sr_bank_modules.begin(), sr_bank_modules.end(), pair.first.first)) {
sr_bank_modules.push_back(pair.first.first);
}
}
}
return sr_bank_modules;
}
std::vector<ModuleId> MemoryBankShiftRegisterBanks::wl_shift_register_bank_modules(const ConfigRegionId& region) const {
std::vector<ModuleId> sr_bank_modules;
VTR_ASSERT(valid_region_id(region));
for (const auto& pair : wl_sr_instance_sink_child_ids_[region]) {
sr_bank_modules.push_back(pair.first.first);
}
return sr_bank_modules;
}
std::vector<size_t> MemoryBankShiftRegisterBanks::wl_shift_register_bank_instances(const ConfigRegionId& region) const {
std::vector<size_t> sr_bank_instances;
VTR_ASSERT(valid_region_id(region));
for (const auto& pair : wl_sr_instance_sink_child_ids_[region]) {
sr_bank_instances.push_back(pair.first.second);
}
return sr_bank_instances;
}
std::vector<size_t> MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = wl_sr_instance_sink_child_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != wl_sr_instance_sink_child_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
std::vector<size_t> MemoryBankShiftRegisterBanks::wl_shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = sr_instance_source_blwl_ids_[region].find(std::make_pair(sr_module, sr_instance));
auto result = wl_sr_instance_sink_child_pin_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != sr_instance_source_blwl_ids_[region].end()) {
if (result != wl_sr_instance_sink_child_pin_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
}
std::vector<size_t> MemoryBankShiftRegisterBanks::wl_shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const {
VTR_ASSERT(valid_region_id(region));
auto result = wl_sr_instance_source_blwl_ids_[region].find(std::make_pair(sr_module, sr_instance));
/* Return an empty vector if not found */
if (result != wl_sr_instance_source_blwl_ids_[region].end()) {
return result->second;
}
return std::vector<size_t>();
@ -133,36 +202,71 @@ std::vector<BasicPort> MemoryBankShiftRegisterBanks::wl_bank_data_ports(const Co
}
void MemoryBankShiftRegisterBanks::resize_regions(const size_t& num_regions) {
sr_instance_sink_child_ids_.resize(num_regions);
sr_instance_sink_child_pin_ids_.resize(num_regions);
sr_instance_source_blwl_ids_.resize(num_regions);
bl_bank_ids_.resize(num_regions);
bl_bank_data_ports_.resize(num_regions);
bl_sr_instance_sink_child_ids_.resize(num_regions);
bl_sr_instance_sink_child_pin_ids_.resize(num_regions);
bl_sr_instance_source_blwl_ids_.resize(num_regions);
wl_bank_ids_.resize(num_regions);
wl_bank_data_ports_.resize(num_regions);
wl_sr_instance_sink_child_ids_.resize(num_regions);
wl_sr_instance_sink_child_pin_ids_.resize(num_regions);
wl_sr_instance_source_blwl_ids_.resize(num_regions);
}
void MemoryBankShiftRegisterBanks::add_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) {
void MemoryBankShiftRegisterBanks::add_bl_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) {
VTR_ASSERT(valid_region_id(region));
sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)];
sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)];
sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)];
bl_sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)];
bl_sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)];
bl_sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)];
}
void MemoryBankShiftRegisterBanks::add_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id) {
void MemoryBankShiftRegisterBanks::add_bl_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id) {
VTR_ASSERT(valid_region_id(region));
sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_id);
sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_pin_id);
bl_sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_id);
bl_sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_pin_id);
}
void MemoryBankShiftRegisterBanks::add_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id) {
void MemoryBankShiftRegisterBanks::add_bl_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id) {
VTR_ASSERT(valid_region_id(region));
sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_blwl_id);
bl_sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_blwl_id);
}
void MemoryBankShiftRegisterBanks::add_wl_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) {
VTR_ASSERT(valid_region_id(region));
wl_sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)];
wl_sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)];
wl_sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)];
}
void MemoryBankShiftRegisterBanks::add_wl_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id) {
VTR_ASSERT(valid_region_id(region));
wl_sr_instance_sink_child_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_id);
wl_sr_instance_sink_child_pin_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_child_pin_id);
}
void MemoryBankShiftRegisterBanks::add_wl_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id) {
VTR_ASSERT(valid_region_id(region));
wl_sr_instance_source_blwl_ids_[region][std::make_pair(sr_module, sr_instance)].push_back(sink_blwl_id);
}
void MemoryBankShiftRegisterBanks::reserve_bl_shift_register_banks(const ConfigRegionId& region_id, const size_t& num_banks) {
@ -215,7 +319,7 @@ void MemoryBankShiftRegisterBanks::add_data_port_to_wl_shift_register_bank(const
bool MemoryBankShiftRegisterBanks::valid_region_id(const ConfigRegionId& region) const {
return size_t(region) < sr_instance_sink_child_ids_.size();
return size_t(region) < bl_sr_instance_sink_child_ids_.size();
}
bool MemoryBankShiftRegisterBanks::valid_bl_bank_id(const ConfigRegionId& region_id, const FabricBitLineBankId& bank_id) const {

128
openfpga/src/fabric/memory_bank_shift_register_banks.h
View File

@ -45,56 +45,68 @@ class MemoryBankShiftRegisterBanks {
std::vector<BasicPort> wl_bank_data_ports(const ConfigRegionId& region_id, const FabricWordLineBankId& bank_id) const;
/* @brief Return a list of modules of unique shift register banks across all the regions */
std::vector<ModuleId> shift_register_bank_unique_modules() const;
std::vector<ModuleId> bl_shift_register_bank_unique_modules() const;
/* @brief Return a list of modules of shift register banks under a specific configuration region of top-level module */
std::vector<ModuleId> shift_register_bank_modules(const ConfigRegionId& region) const;
std::vector<ModuleId> bl_shift_register_bank_modules(const ConfigRegionId& region) const;
/* @brief Return a list of instances of shift register banks under a specific configuration region of top-level module */
std::vector<size_t> shift_register_bank_instances(const ConfigRegionId& region) const;
std::vector<size_t> bl_shift_register_bank_instances(const ConfigRegionId& region) const;
/* @brief Return a list of ids of reconfigurable children for a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
std::vector<size_t> bl_shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of BL/WL ids of reconfigurable children for a given instance of shift register bank
/* @brief Return a list of BL ids of reconfigurable children for a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of BL/WL ids of a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
std::vector<size_t> bl_shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of BL ids of a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> bl_shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of modules of unique shift register banks across all the regions */
std::vector<ModuleId> wl_shift_register_bank_unique_modules() const;
/* @brief Return a list of modules of shift register banks under a specific configuration region of top-level module */
std::vector<ModuleId> wl_shift_register_bank_modules(const ConfigRegionId& region) const;
/* @brief Return a list of instances of shift register banks under a specific configuration region of top-level module */
std::vector<size_t> wl_shift_register_bank_instances(const ConfigRegionId& region) const;
/* @brief Return a list of ids of reconfigurable children for a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> wl_shift_register_bank_sink_child_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of WL ids of reconfigurable children for a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> wl_shift_register_bank_sink_pin_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
/* @brief Return a list of WL ids of a given instance of shift register bank
* under a specific configuration region of top-level module
*/
std::vector<size_t> wl_shift_register_bank_source_blwl_ids(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance) const;
public: /* Mutators */
void resize_regions(const size_t& num_regions);
/* @brief Add the module id and instance id of a shift register under a specific configuration region of top-level module */
void add_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance);
/* @brief Add the child id and pin id of BL/WL to which a shift register is connected to under a specific configuration region of top-level module */
void add_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id);
/* @brief Add the BL/WL id under a specific configuration region of top-level module to which a shift register is connected to */
void add_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id);
/* Reserve a number of banks to be memory efficent */
void reserve_bl_shift_register_banks(const ConfigRegionId& region_id, const size_t& num_banks);
void reserve_wl_shift_register_banks(const ConfigRegionId& region_id, const size_t& num_banks);
@ -115,6 +127,42 @@ class MemoryBankShiftRegisterBanks {
const FabricWordLineBankId& bank_id,
const openfpga::BasicPort& data_port);
/* @brief Add the module id and instance id of a shift register under a specific configuration region of top-level module */
void add_bl_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance);
/* @brief Add the child id and pin id of BL to which a shift register is connected to under a specific configuration region of top-level module */
void add_bl_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id);
/* @brief Add the BL id under a specific configuration region of top-level module to which a shift register is connected to */
void add_bl_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id);
/* @brief Add the module id and instance id of a shift register under a specific configuration region of top-level module */
void add_wl_shift_register_instance(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance);
/* @brief Add the child id and pin id of WL to which a shift register is connected to under a specific configuration region of top-level module */
void add_wl_shift_register_sink_nodes(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_child_id,
const size_t& sink_child_pin_id);
/* @brief Add the BL/WL id under a specific configuration region of top-level module to which a shift register is connected to */
void add_wl_shift_register_source_blwls(const ConfigRegionId& region,
const ModuleId& sr_module,
const size_t& sr_instance,
const size_t& sink_blwl_id);
public: /* Validators */
bool valid_region_id(const ConfigRegionId& region) const;
bool valid_bl_bank_id(const ConfigRegionId& region_id, const FabricBitLineBankId& bank_id) const;
@ -125,14 +173,20 @@ class MemoryBankShiftRegisterBanks {
vtr::vector<ConfigRegionId, vtr::vector<FabricBitLineBankId, FabricBitLineBankId>> bl_bank_ids_;
vtr::vector<ConfigRegionId, vtr::vector<FabricBitLineBankId, std::vector<BasicPort>>> bl_bank_data_ports_;
/* BL: [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> bl_sr_instance_sink_child_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> bl_sr_instance_sink_child_pin_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> bl_sr_instance_source_blwl_ids_;
/* General information about the WL shift register bank */
vtr::vector<ConfigRegionId, vtr::vector<FabricWordLineBankId, FabricWordLineBankId>> wl_bank_ids_;
vtr::vector<ConfigRegionId, vtr::vector<FabricWordLineBankId, std::vector<BasicPort>>> wl_bank_data_ports_;
/* [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_sink_child_pin_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> sr_instance_source_blwl_ids_;
/* WL: [config_region][(shift_register_module, shift_register_instance)][i] = (reconfigurable_child_id, blwl_port_pin_index)*/
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> wl_sr_instance_sink_child_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> wl_sr_instance_sink_child_pin_ids_;
vtr::vector<ConfigRegionId, std::map<std::pair<ModuleId, size_t>, std::vector<size_t>>> wl_sr_instance_source_blwl_ids_;
};
} /* end namespace openfpga */

2
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -55,7 +55,7 @@ namespace openfpga {
********************************************************************/
void fpga_fabric_verilog(ModuleManager &module_manager,
NetlistManager &netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary &circuit_lib,
const MuxLibrary &mux_lib,
const DecoderLibrary &decoder_lib,

2
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -36,7 +36,7 @@ namespace openfpga {
void fpga_fabric_verilog(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const DecoderLibrary& decoder_lib,

31
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -34,7 +34,7 @@ namespace openfpga {
********************************************************************/
void print_verilog_submodule_shift_register_banks(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const std::string& submodule_dir,
const FabricVerilogOption& options) {
@ -54,17 +54,26 @@ void print_verilog_submodule_shift_register_banks(const ModuleManager& module_ma
print_verilog_file_header(fp, "Shift register banks used in FPGA");
/* Create the memory circuits for the multiplexer */
for (const auto& sr_bank : blwl_sr_banks) {
for (const ModuleId& sr_module : sr_bank.shift_register_bank_unique_modules()) {
VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.default_net_type());
for (const ModuleId& sr_module : blwl_sr_banks.bl_shift_register_bank_unique_modules()) {
VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
}
/* Add an empty line as a splitter */
fp << std::endl;
}
for (const ModuleId& sr_module : blwl_sr_banks.wl_shift_register_bank_unique_modules()) {
VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, sr_module,
options.explicit_port_mapping(),
options.default_net_type());
/* Add an empty line as a splitter */
fp << std::endl;
}
/* Close the file stream */

2
openfpga/src/fpga_verilog/verilog_shift_register_banks.h
View File

@ -20,7 +20,7 @@ namespace openfpga {
void print_verilog_submodule_shift_register_banks(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const std::string& submodule_dir,
const FabricVerilogOption& options);

2
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -34,7 +34,7 @@ namespace openfpga {
********************************************************************/
void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const MuxLibrary& mux_lib,
const DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,

2
openfpga/src/fpga_verilog/verilog_submodule.h
View File

@ -20,7 +20,7 @@ namespace openfpga {
void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const MuxLibrary& mux_lib,
const DecoderLibrary& decoder_lib,
const CircuitLibrary& circuit_lib,

2
openfpga/src/utils/fabric_bitstream_utils.cpp
View File

@ -399,7 +399,7 @@ std::vector<std::string> reshape_bitstream_vectors_to_first_element(const std::v
MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
//const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const bool& bit_value_to_skip,
const char& dont_care_bit) {
MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip, dont_care_bit);

2
openfpga/src/utils/fabric_bitstream_utils.h
View File

@ -96,7 +96,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
*******************************************************************/
MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
//const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const bool& bit_value_to_skip,
const char& dont_care_bit = 'x');