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[FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path``

This commit is contained in:
tangxifan 2022-02-01 13:25:09 -08:00
parent b7b0a2a5d8
commit 1c94d0f285
4 changed files with 14 additions and 3 deletions
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2
openfpga/src/base/openfpga_verilog.cpp
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@ -197,6 +197,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_use_relative_path = cmd.option("use_relative_path");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -208,6 +209,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_use_relative_path(cmd_context.option_enable(cmd, opt_use_relative_path));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {

3
openfpga/src/base/openfpga_verilog_command.cpp
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@ -224,6 +224,9 @@ ShellCommandId add_openfpga_write_preconfigured_testbench_command(openfpga::Shel
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* Add an option '--use_relative_path' */
shell_cmd.add_option("use_relative_path", false, "Force to use relative path in netlists when including other netlists");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");

10
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
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@ -154,10 +154,10 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir_pa
* that have been generated and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir_path,
const std::string& circuit_name,
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string verilog_fname = src_dir_path + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
@ -172,6 +172,12 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* If relative path is forced, we do not include an src_dir_path in the netlist */
std::string src_dir = src_dir_path;
if (options.use_relative_path()) {
src_dir.clear();
}
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
if (true == fabric_netlist_file.empty()) {

2
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
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@ -27,7 +27,7 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir_pa
const std::string& circuit_name,
const VerilogTestbenchOption& options);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir_path,
const std::string& circuit_name,
const VerilogTestbenchOption& options);