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[FPGA-Verilog] Fixed a bug on config-enable signals

This commit is contained in:
tangxifan 2022-02-23 22:35:23 -08:00
parent e443a4567d
commit 235887e03a
1 changed files with 2 additions and 0 deletions
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2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
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@ -237,6 +237,8 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp,
std::vector<size_t> default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id));
/* For configuration done signals, we should enable them in preconfigured wrapper */
if (fabric_global_ports.global_port_is_config_enable(global_port_id)) {
VTR_LOG("Config-enable port '%s' is detected with default value '%ld'", module_global_pin.get_name().c_str(), fabric_global_ports.global_port_default_value(global_port_id));
default_values.clear();
default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id));
}
print_verilog_wire_constant_values(fp, module_global_pin, default_values);