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[engine] debugging

This commit is contained in:
tangxifan 2022-08-17 14:37:13 -07:00
parent 8f1aac885e
commit 3c12810ad9
2 changed files with 2 additions and 2 deletions
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2
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
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@ -364,7 +364,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager
/* No bitstream generation required by a special direct connection*/
} else if (1 < driver_rr_nodes.size()) {
/* Create the block denoting the memory instances that drives this node in Switch Block */
std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_graph.node_side(src_rr_node), ipin_index, std::string(""));
std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, get_rr_graph_single_node_side(rr_graph, src_rr_node), ipin_index, std::string(""));
ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name);
bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block);
/* This is a routing multiplexer! Generate bitstream */

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit b54d4ad4f3e6bbd0e54a567be3921fdd30efed4d
Subproject commit 885eb58feef2d0fb6789cff017803e032bc3ee82