From 3c12810ad98a671cc355d6f2cc40739e8de8a82e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Aug 2022 14:37:13 -0700 Subject: [PATCH] [engine] debugging --- openfpga/src/fpga_bitstream/build_routing_bitstream.cpp | 2 +- vtr-verilog-to-routing | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index 28230c01e..308987355 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -364,7 +364,7 @@ void build_connection_block_interc_bitstream(BitstreamManager& bitstream_manager /* No bitstream generation required by a special direct connection*/ } else if (1 < driver_rr_nodes.size()) { /* Create the block denoting the memory instances that drives this node in Switch Block */ - std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, rr_graph.node_side(src_rr_node), ipin_index, std::string("")); + std::string mem_block_name = generate_cb_memory_instance_name(CONNECTION_BLOCK_MEM_INSTANCE_PREFIX, get_rr_graph_single_node_side(rr_graph, src_rr_node), ipin_index, std::string("")); ConfigBlockId mux_mem_block = bitstream_manager.add_block(mem_block_name); bitstream_manager.add_child_block(cb_configurable_block, mux_mem_block); /* This is a routing multiplexer! Generate bitstream */ diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index b54d4ad4f..885eb58fe 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit b54d4ad4f3e6bbd0e54a567be3921fdd30efed4d +Subproject commit 885eb58feef2d0fb6789cff017803e032bc3ee82