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[engine] fixing mismatches in APIs

This commit is contained in:
tangxifan 2022-08-17 14:19:02 -07:00
parent 4e871be357
commit 8f1aac885e
12 changed files with 76 additions and 66 deletions
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15
CMakeLists.txt
View File

@ -44,7 +44,6 @@ project("OPENFPGA" C CXX)
# Options
# Option to enable/disable graphic in compilation
option(ENABLE_VPR_GRAPHICS "Enables VPR graphics" ON)
option(ENABLE_VPR_GRAPHICS "Enables build with librtlnumber" OFF)
#Allow the user to decide weather to compile the graphics library
set(VPR_USE_EZGL "auto" CACHE STRING "Specify whether vpr uses the graphics library")
@ -75,6 +74,11 @@ set(CMAKE_CXX_STANDARD 14)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions
if(NOT MSVC)
# for GCC and Clang
set(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -O0 -g3")
set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -O0 -g3")
endif()
# Set WARN FLAGS
set(WARN_FLAGS "")
@ -88,13 +92,6 @@ if (MSVC)
else ()
set(WARN_FLAGS_TO_CHECK # the flags to check if the compiler supports
#GCC-like
"-Wpointer-arith"
"-Wcast-qual"
"-D__USE_FIXED_PROTOTYPES__"
"-ansi"
"-Wshadow"
"-Wno-write-strings"
"-D_POSIX_SOURCE"
"-Wall" #Most warnings, typically good
"-Wextra" #Extra warning, usually good
"-Wpedantic" #Ensure ISO compliance (i.e. no non-standard extensions)
@ -124,7 +121,7 @@ else ()
"-Winit-self" #Warn about self-initialization
"-Wcatch-value=3" #Warn when catch statements don't catch by reference
"-Wextra-semi" #Warn about redudnant semicolons
"-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
"-Wimplicit-fallthrough=4" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
#GCC-like optional
#"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods
#"-Wsuggest-final-methods" #Suggest where 'final' would help if specified on methods

84
libopenfpga/libopenfpgautil/src/openfpga_reserved_words.h
View File

@ -11,67 +11,67 @@
namespace openfpga {
/* Top-level module name */
constexpr char* FPGA_TOP_MODULE_NAME = "fpga_top";
constexpr const char* FPGA_TOP_MODULE_NAME = "fpga_top";
/* Configuration chain naming constant strings */
constexpr char* CONFIGURABLE_MEMORY_CHAIN_IN_NAME = "ccff_head";
constexpr char* CONFIGURABLE_MEMORY_CHAIN_OUT_NAME = "ccff_tail";
constexpr char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out";
constexpr char* CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME = "mem_outb";
constexpr char* BL_SHIFT_REGISTER_CHAIN_HEAD_NAME = "bl_sr_head";
constexpr char* BL_SHIFT_REGISTER_CHAIN_TAIL_NAME = "bl_sr_tail";
constexpr char* BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME = "bl_sr_bl_out";
constexpr char* WL_SHIFT_REGISTER_CHAIN_HEAD_NAME = "wl_sr_head";
constexpr char* WL_SHIFT_REGISTER_CHAIN_TAIL_NAME = "wl_sr_tail";
constexpr char* WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME = "wl_sr_wl_out";
constexpr char* WL_SHIFT_REGISTER_CHAIN_WLR_OUT_NAME = "wl_sr_wlr_out";
constexpr const char* CONFIGURABLE_MEMORY_CHAIN_IN_NAME = "ccff_head";
constexpr const char* CONFIGURABLE_MEMORY_CHAIN_OUT_NAME = "ccff_tail";
constexpr const char* CONFIGURABLE_MEMORY_DATA_OUT_NAME = "mem_out";
constexpr const char* CONFIGURABLE_MEMORY_INVERTED_DATA_OUT_NAME = "mem_outb";
constexpr const char* BL_SHIFT_REGISTER_CHAIN_HEAD_NAME = "bl_sr_head";
constexpr const char* BL_SHIFT_REGISTER_CHAIN_TAIL_NAME = "bl_sr_tail";
constexpr const char* BL_SHIFT_REGISTER_CHAIN_BL_OUT_NAME = "bl_sr_bl_out";
constexpr const char* WL_SHIFT_REGISTER_CHAIN_HEAD_NAME = "wl_sr_head";
constexpr const char* WL_SHIFT_REGISTER_CHAIN_TAIL_NAME = "wl_sr_tail";
constexpr const char* WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME = "wl_sr_wl_out";
constexpr const char* WL_SHIFT_REGISTER_CHAIN_WLR_OUT_NAME = "wl_sr_wlr_out";
/* IO PORT */
/* Prefix of global input, output and inout ports of FPGA fabric */
constexpr char* GIO_INOUT_PREFIX = "gfpga_pad_";
constexpr const char* GIO_INOUT_PREFIX = "gfpga_pad_";
/* Grid naming constant strings */
constexpr char* GRID_MODULE_NAME_PREFIX = "grid_";
constexpr char* LOGICAL_MODULE_NAME_PREFIX = "logical_tile_";
constexpr const char* GRID_MODULE_NAME_PREFIX = "grid_";
constexpr const char* LOGICAL_MODULE_NAME_PREFIX = "logical_tile_";
/* Memory naming constant strings */
constexpr char* GRID_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr char* MEMORY_MODULE_POSTFIX = "_mem";
constexpr char* MEMORY_BL_PORT_NAME = "bl";
constexpr char* MEMORY_WL_PORT_NAME = "wl";
constexpr char* MEMORY_WLR_PORT_NAME = "wlr";
constexpr const char* GRID_MEM_INSTANCE_PREFIX = "mem_";
constexpr const char* SWITCH_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr const char* CONNECTION_BLOCK_MEM_INSTANCE_PREFIX = "mem_";
constexpr const char* MEMORY_MODULE_POSTFIX = "_mem";
constexpr const char* MEMORY_BL_PORT_NAME = "bl";
constexpr const char* MEMORY_WL_PORT_NAME = "wl";
constexpr const char* MEMORY_WLR_PORT_NAME = "wlr";
/* Multiplexer naming constant strings */
constexpr char* MUX_BASIS_MODULE_POSTFIX = "_basis";
constexpr char* GRID_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
constexpr char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
constexpr const char* MUX_BASIS_MODULE_POSTFIX = "_basis";
constexpr const char* GRID_MUX_INSTANCE_PREFIX = "mux_";
constexpr const char* SWITCH_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
constexpr const char* CONNECTION_BLOCK_MUX_INSTANCE_PREFIX = "mux_";
/* Decoder naming constant strings */
constexpr char* DECODER_ENABLE_PORT_NAME = "enable";
constexpr char* DECODER_ADDRESS_PORT_NAME = "address";
constexpr char* DECODER_DATA_IN_PORT_NAME = "data_in";
constexpr char* DECODER_DATA_OUT_PORT_NAME = "data_out";
constexpr char* DECODER_DATA_OUT_INV_PORT_NAME = "data_out_inv";
constexpr char* DECODER_BL_ADDRESS_PORT_NAME = "bl_address";
constexpr char* DECODER_WL_ADDRESS_PORT_NAME = "wl_address";
constexpr char* DECODER_READBACK_PORT_NAME = "readback";
constexpr char* DECODER_DATA_READ_ENABLE_PORT_NAME = "data_out_ren";
constexpr const char* DECODER_ENABLE_PORT_NAME = "enable";
constexpr const char* DECODER_ADDRESS_PORT_NAME = "address";
constexpr const char* DECODER_DATA_IN_PORT_NAME = "data_in";
constexpr const char* DECODER_DATA_OUT_PORT_NAME = "data_out";
constexpr const char* DECODER_DATA_OUT_INV_PORT_NAME = "data_out_inv";
constexpr const char* DECODER_BL_ADDRESS_PORT_NAME = "bl_address";
constexpr const char* DECODER_WL_ADDRESS_PORT_NAME = "wl_address";
constexpr const char* DECODER_READBACK_PORT_NAME = "readback";
constexpr const char* DECODER_DATA_READ_ENABLE_PORT_NAME = "data_out_ren";
/* Inverted port naming */
constexpr char* INV_PORT_POSTFIX = "_inv";
constexpr const char* INV_PORT_POSTFIX = "_inv";
/* Bitstream file strings */
constexpr char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
constexpr const char* BITSTREAM_XML_FILE_NAME_POSTFIX = "_bitstream.xml";
constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
constexpr const char* DEFAULT_LB_DIR_NAME = "lb/";
constexpr const char* DEFAULT_RR_DIR_NAME = "routing/";
constexpr const char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
constexpr char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
constexpr const char* VPR_BENCHMARK_OUT_PORT_PREFIX = "out:";
constexpr const char* OPENFPGA_BENCHMARK_OUT_PORT_PREFIX = "out_";
} /* end namespace openfpga */

2
libopenfpga/libpcf/src/base/pin_constraints.h
View File

@ -18,7 +18,7 @@
#include "pin_constraints_fwd.h"
/* Constants */
constexpr char* PIN_CONSTRAINT_OPEN_NET = "OPEN";
constexpr const char* PIN_CONSTRAINT_OPEN_NET = "OPEN";
/********************************************************************
* A data structure to describe the pin constraints for FPGA fabrics

2
libopenfpga/libpcf/src/base/repack_design_constraints.h
View File

@ -18,7 +18,7 @@
#include "repack_design_constraints_fwd.h"
/* Constants */
constexpr char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN";
constexpr const char* REPACK_DESIGN_CONSTRAINT_OPEN_NET = "OPEN";
/********************************************************************
* A data structure to describe the design constraints for repacking tools

1
openfpga/src/annotation/annotate_simulation_setting.h
View File

@ -15,6 +15,7 @@
namespace openfpga {
int annotate_simulation_setting(const AtomContext& atom_ctx,
const ClusteringContext& cluster_ctx,
const std::unordered_map<AtomNetId, t_net_power>& net_activity,
SimulationSetting& sim_setting);

1
openfpga/src/base/openfpga_link_arch.cpp
View File

@ -174,6 +174,7 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
*/
//openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
g_vpr_ctx.clustering(),
net_activity,
openfpga_ctx.mutable_simulation_setting())) {
return CMD_EXEC_FATAL_ERROR;

8
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -86,8 +86,8 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
}
/* Find the net mapped to this pin in routing results */
const RRNodeId& rr_node = device_ctx.rr_graph.find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side);
if (false == device_ctx.rr_graph.valid_node_id(rr_node)) {
const RRNodeId& rr_node = device_ctx.rr_graph.node_lookup().find_node(grid_coord.x(), grid_coord.y(), rr_node_type, physical_pin, pin_side);
if (false == device_ctx.rr_graph.valid_node(rr_node)) {
continue;
}
/* Get the cluster net id which has been mapped to this net */
@ -198,7 +198,7 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
vpr_routing_annotation,
vpr_clustering_annotation,
grid_coord, cluster_blk_id, NUM_SIDES,
placement_ctx.block_locs[cluster_blk_id].loc.z,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
verbose);
}
}
@ -246,7 +246,7 @@ void update_pb_pin_with_post_routing_results(const DeviceContext& device_ctx,
vpr_routing_annotation,
vpr_clustering_annotation,
io_coord, cluster_blk_id, io_side,
placement_ctx.block_locs[cluster_blk_id].loc.z,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile,
verbose);
}
}

4
openfpga/src/fabric/build_grid_module_duplicated_pins.cpp
View File

@ -255,7 +255,9 @@ void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
for (t_logical_block_type_ptr lb_type : grid_type_descriptor->equivalent_sites) {
/* FIXME: Currently support only 1 equivalent site! Should clarify this limitation in documentation! */
for (const t_sub_tile& sub_tile : grid_type_descriptor->sub_tiles) {
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);

20
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -109,7 +109,10 @@ void add_grid_module_nets_connect_pb_type_ports(ModuleManager& module_manager,
/* Ensure that we have a valid grid_type_descriptor */
VTR_ASSERT(nullptr != grid_type_descriptor);
for (t_logical_block_type_ptr lb_type : grid_type_descriptor->equivalent_sites) {
/* FIXME: Currently support only 1 equivalent site! Should clarify this limitation in documentation! */
for (const t_sub_tile& sub_tile : grid_type_descriptor->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
VTR_ASSERT(nullptr != top_pb_graph_node);
@ -1009,9 +1012,10 @@ void build_physical_tile_module(ModuleManager& module_manager,
* If you need different equivalent sites, you can always define
* it as a mode under a <pb_type>
*/
for (int iz = 0; iz < phy_block_type->capacity; ++iz) {
VTR_ASSERT(1 == phy_block_type->equivalent_sites.size());
for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
for (int iz = 0; iz < sub_tile.capacity.total(); ++iz) {
VTR_ASSERT(1 == sub_tile.equivalent_sites.size());
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
/* Bypass empty pb_graph */
if (nullptr == lb_type->pb_graph_head) {
continue;
@ -1047,7 +1051,9 @@ void build_physical_tile_module(ModuleManager& module_manager,
vpr_device_annotation,
phy_block_type, border_side);
/* Add module nets to connect the pb_type ports to sub modules */
for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
/* Bypass empty pb_graph */
if (nullptr == lb_type->pb_graph_head) {
continue;
@ -1070,7 +1076,9 @@ void build_physical_tile_module(ModuleManager& module_manager,
phy_block_type, border_side);
/* Add module nets to connect the duplicated pb_type ports to sub modules */
for (t_logical_block_type_ptr lb_type : phy_block_type->equivalent_sites) {
for (const t_sub_tile& sub_tile : phy_block_type->sub_tiles) {
VTR_ASSERT(sub_tile.equivalent_sites.size() == 1);
t_logical_block_type_ptr lb_type = sub_tile.equivalent_sites[0];
/* Bypass empty pb_graph */
if (nullptr == lb_type->pb_graph_head) {
continue;

1
openfpga/src/fabric/memory_bank_shift_register_banks.h
View File

@ -5,6 +5,7 @@
#include <vector>
#include "vtr_vector.h"
#include "fabric_key.h"
#include "openfpga_port.h"
#include "module_manager.h"
/* begin namespace openfpga */

2
openfpga/src/fpga_bitstream/build_io_mapping_info.cpp
View File

@ -81,7 +81,7 @@ IoMap build_fpga_io_mapping_info(const ModuleManager& module_manager,
/* Find the index of the mapped GPIO in top-level FPGA fabric */
size_t temp_io_index = io_location_map.io_index(place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.x,
place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.y,
place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.z,
place_ctx.block_locs[atom_ctx.lookup.atom_clb(atom_blk)].loc.sub_tile,
module_io_port.get_name());
/* Bypass invalid index (not mapped to this GPIO port) */

2
openfpga/src/utils/rr_gsb_utils.h
View File

@ -18,7 +18,7 @@ namespace openfpga {
bool connection_block_contain_only_routing_tracks(const RRGSB& rr_gsb,
const t_rr_type& cb_type);
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraphViewView& rr_graph,
std::vector<RRNodeId> get_rr_gsb_chan_node_configurable_driver_nodes(const RRGraphView& rr_graph,
const RRGSB& rr_gsb,
const e_side& chan_side,
const size_t& track_id);